Simple, efficient. fast, low resource DMA TX #2844
Open
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Requirements
BTT or MKS TFT
Description
This PR implements DMA transmit for serial ports as opposite to the current direct (CPU-managed) mode.
Direct Memory Access (DMA) for USART transfer is often considered better than direct (CPU-managed) USART transfers for several reasons. Those applicable to this TFT firmware are:
Offloading CPU: DMA allows the UART communication to occur with minimal CPU intervention. In a direct transfer, the CPU is typically responsible for managing data transfer, which can be resource-intensive and slow down other tasks the CPU needs to perform. With DMA, the CPU sets up the transfer and then lets the DMA controller handle the data movement, freeing up the CPU for other tasks.
Improved Efficiency: DMA controllers are specifically designed to handle data transfers efficiently, with minimal overhead. This can result in faster and more efficient data transfers, especially for larger chunks of data.
Reduced Latency: With direct transfers, the CPU may introduce additional latency in servicing USART requests, leading to delays in data transfer. DMA transfers can significantly reduce this latency, as they can handle data transfers without interrupting the CPU for each byte or character.
Consistency: DMA transfers provide a level of consistency and predictability in data transfer rates, which is beneficial in real-time or time-critical applications. CPU-managed transfers can vary in speed depending on the CPU's current workload.
Multi-Channel Capability: DMA controllers support multiple channels, allowing for concurrent data transfers between different peripherals or memory locations. This is particularly useful in complex embedded systems with multiple communication peripherals (read and write from/to several serial ports at the same time such as of WiFi module, printer, etc.)
Benefits
Based on real tests it frees up more than 20% of the CPU load during print.
Notes