fixup! Fixes(?) to reset paths, ready reporting, and CC reset detection.

bittide · Oct 30, 2024 · 0c2fc0d · 0c2fc0d
1 parent 1722058
commit 0c2fc0d
Showing 1 changed file with 6 additions and 7 deletions.
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs b/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs
@@ -253,10 +253,7 @@ topologyTest refClk sysClk sysRst IlaControl{syncRst = rst, ..} rxNs rxPs miso c
     , repeat $ pure True
     )
  where
-  syncRst =
-    rst
-      `orReset` unsafeFromActiveHigh spiErr
-      `orReset` unsafeFromActiveLow spiDone
+  syncRst = rst `orReset` unsafeFromActiveHigh spiErr
 
   -- Clock board programming
   spiDone = E.dflipflop sysClk $ (== Finished) <$> spiState
@@ -269,6 +266,8 @@ topologyTest refClk sysClk sysRst IlaControl{syncRst = rst, ..} rxNs rxPs miso c
     withClockResetEnable sysClk syncRst enableGen
       $ si539xSpi commonSpiConfig (SNat @(Microseconds 10)) (pure Nothing) miso
 
+  gthAllReset = unsafeFromActiveLow spiDone
+
   transceivers =
     transceiverPrbsN
       @GthTx
@@ -280,14 +279,14 @@ topologyTest refClk sysClk sysRst IlaControl{syncRst = rst, ..} rxNs rxPs miso c
       Transceiver.defConfig
       Transceiver.Inputs
         { clock = sysClk
-        , reset = syncRst
+        , reset = gthAllReset
         , refClock = refClk
         , channelNames
         , clockPaths
         , rxNs
         , rxPs
-        -- , txDatas = txCounters
-        , txDatas = repeat $ pure 0
+        , txDatas = txCounters
+        -- , txDatas = repeat $ pure 0
         , txReadys = repeat (pure False)
         , rxReadys = repeat (pure True)
         }