Make wishbone addressing word based

Byte based addressing has up to now only added complexity

bittide-instances/src/Bittide/Instances/Hitl/FullMeshHwCc.hs

@@ -122,7 +122,7 @@ fullMeshRiscvCopyTest clk rst callistoResult dataCounts = unbundle fIncDec
 
   fIncDecCallisto ::
     forall aw nBytes.
-    (KnownNat aw, 2 <= aw, nBytes ~ 4) =>
+    (KnownNat aw, nBytes ~ 4) =>
     Circuit
       (Wishbone dom 'Standard aw (Bytes nBytes))
       ()

bittide-instances/src/Bittide/Instances/Hitl/HwCcTopologies.hs

@@ -234,7 +234,7 @@ riscvCopyTest clk rst callistoResult dataCounts = unbundle fIncDec
 
   fIncDecCallisto ::
     forall aw nBytes.
-    (KnownNat aw, 2 <= aw, nBytes ~ 4) =>
+    (KnownNat aw, nBytes ~ 4) =>
     Circuit
       (Wishbone dom 'Standard aw (Bytes nBytes))
       ()

bittide-instances/src/Bittide/Instances/Hitl/VexRiscv.hs

@@ -68,7 +68,7 @@ vexRiscvInner jtagIn0 uartRx =
     testResult <- statusRegister -< statusRegisterBus
     idC -< (testResult, uartTx)
 
-  statusRegister :: Circuit (Wishbone dom 'Standard 29 (Bytes 4)) (CSignal dom TestStatus)
+  statusRegister :: Circuit (Wishbone dom 'Standard 27 (Bytes 4)) (CSignal dom TestStatus)
   statusRegister = Circuit $ \(fwd, _) ->
     let (unbundle -> (m2s, st)) = mealy go Running fwd
      in (m2s, st)

bittide/src/Bittide/Axi4.hs

@@ -198,7 +198,6 @@ wbAxisRxBufferCircuit ::
   forall dom wbAddrW wbBytes bufferBytes.
   ( HiddenClockResetEnable dom
   , KnownNat wbAddrW
-  , 2 <= wbAddrW
   , KnownNat wbBytes
   , 1 <= wbBytes
   , 1 <= bufferBytes
@@ -225,7 +224,6 @@ wbAxisRxBuffer ::
   forall dom wbAddrW wbBytes bufferBytes.
   ( HiddenClockResetEnable dom
   , KnownNat wbAddrW
-  , 2 <= wbAddrW
   , KnownNat wbBytes
   , 1 <= wbBytes
   , 1 <= bufferBytes
@@ -271,7 +269,6 @@ wbAxisRxBuffer# ::
   forall dom wbAddrW wbBytes fifoDepth.
   ( HiddenClockResetEnable dom
   , KnownNat wbAddrW
-  , 2 <= wbAddrW
   , KnownNat wbBytes
   , 1 <= wbBytes
   , 1 <= fifoDepth
@@ -332,12 +329,10 @@ wbAxisRxBuffer# fifoDepth@SNat wbM2S axisM2S = (wbS2M, axisS2M, statusReg)
       (newState, output)
      where
       masterActive = busCycle && strobe
-      (alignedAddress, alignment) = split @_ @(wbAddrW - 2) @2 addr
-
       packetLengthAddress = maxBound - 1
       statusAddress = maxBound
-      internalAddress = (bitCoerce $ resize alignedAddress) :: Index (fifoDepth + 2)
-      err = masterActive && (alignment /= 0 || alignedAddress > resize (pack statusAddress))
+      internalAddress = (unpack $ resize addr) :: Index (fifoDepth + 2)
+      err = masterActive && (addr > resize (pack statusAddress))
 
       statusBV = pack (packetComplete, bufferFull)
       wbHandshake = masterActive && not err
@@ -502,11 +497,11 @@ rxReadMaster# SNat = mealyB go (AwaitingData @fifoDepth @wbBytes, Idle)
      where
       -- Driving wishbone signals
       (writeEnable, addr) = case readState of
-        Idle -> (False, natToNum @(4 * (1 + fifoDepth)))
-        ClearingStatus -> (True, natToNum @(4 * (1 + fifoDepth)))
-        ReadingPacketSize -> (False, natToNum @(4 * fifoDepth))
-        ClearingPacketLength -> (True, natToNum @(4 * fifoDepth))
-        ReadingPacket i -> (False, 4 * checkedResize (pack i))
+        Idle -> (False, natToNum @(1 + fifoDepth))
+        ClearingStatus -> (True, natToNum @(1 + fifoDepth))
+        ReadingPacketSize -> (False, natToNum @fifoDepth)
+        ClearingPacketLength -> (True, natToNum @fifoDepth)
+        ReadingPacket i -> (False, checkedResize (pack i))
 
       wbM2S = WishboneM2S{..}
       busCycle = True
@@ -586,10 +581,7 @@ is created that contains no data, but has the _tlast bit set.
 -}
 wbToAxiTx ::
   forall dom addrW nBytes.
-  ( KnownNat addrW
-  , 2 <= addrW
-  , KnownNat nBytes
-  ) =>
+  (KnownNat addrW, KnownNat nBytes) =>
   Circuit
     (Wishbone dom 'Standard addrW (Bytes nBytes))
     (Axi4Stream dom (AxiStreamBytesOnly nBytes) ())
@@ -599,16 +591,15 @@ wbToAxiTx = case cancelMulDiv @nBytes @8 of
     go (WishboneM2S{..}, Axi4StreamS2M{..}) =
       (WishboneS2M{readData, err, acknowledge, retry, stall}, axiM2S)
      where
-      (internalAddress, alignment) = split @_ @(addrW - 2) @2 addr
       masterActive = busCycle && strobe
-      addrValid = shiftR internalAddress 1 == 0 && alignment == 0
+      addrValid = addr <= 1
       err = masterActive && not (addrValid && writeEnable)
       acknowledge = masterActive && not err && _tready
       readData = 0
       retry = False
       stall = False
       (_tkeep, _tlast)
-        | lsb internalAddress == 0 = (reverse $ unpack busSelect, False)
+        | lsb addr == 0 = (reverse $ unpack busSelect, False)
         | otherwise = (repeat False, True)
 
       _tstrb = repeat False

bittide/src/Bittide/Calendar.hs

@@ -104,7 +104,6 @@ mkCalendar ::
   , KnownNat nBytes
   , 1 <= nBytes
   , KnownNat addrW
-  , 2 <= addrW
   ) =>
   -- | Calendar configuration for 'calendar'.
   CalendarConfig nBytes addrW calEntry ->
@@ -178,7 +177,6 @@ calendar ::
   forall dom nBytes addrW maxCalDepth a repetitionBits bootstrapSizeA bootstrapSizeB.
   ( HiddenClockResetEnable dom
   , KnownNat addrW
-  , 2 <= addrW
   , KnownNat bootstrapSizeA
   , 1 <= bootstrapSizeA
   , KnownNat bootstrapSizeB
@@ -374,7 +372,6 @@ wbCalRX ::
   , KnownNat calDepth
   , 2 <= calDepth
   , KnownNat addrW
-  , 2 <= addrW
   , KnownNat nBytes
   , 1 <= nBytes
   ) =>
@@ -401,13 +398,8 @@ wbCalRX = case oneLeCLog2n @calDepth of
      where
       calEntryRegs = natToNum @(Regs calEntry (nBytes * 8))
 
-      (alignedAddress, alignment) = split @_ @(addrW - 2) @2 addr
-      wbAddrValid =
-        alignedAddress
-          <= resize (pack (maxBound :: WbAddress calEntry nBytes))
-          && alignment
-          == 0
-      wishboneAddress = bitCoerce $ resize alignedAddress
+      wbAddrValid = addr <= (resize $ pack (maxBound :: WbAddress calEntry nBytes))
+      wishboneAddress = unpack $ resize addr
       wishboneActive = busCycle && strobe
       wishboneError = wishboneActive && not wbAddrValid
       wbWriting = wishboneActive && writeEnable && not wishboneError

bittide/src/Bittide/ClockControl/Registers.hs

@@ -39,7 +39,6 @@ clockControlWb ::
   forall dom addrW nLinks m margin framesize.
   ( HiddenClockResetEnable dom
   , KnownNat addrW
-  , 2 <= addrW
   , 1 <= framesize
   , 1 <= nLinks
   , KnownNat nLinks

bittide/src/Bittide/DoubleBufferedRam.hs

@@ -107,9 +107,7 @@ wbStorageDPC ::
   forall dom depth awA awB.
   ( HiddenClockResetEnable dom
   , KnownNat awA
-  , 2 <= awA
   , KnownNat awB
-  , 2 <= awB
   , KnownNat depth
   , 1 <= depth
   ) =>
@@ -142,9 +140,7 @@ wbStorageDP ::
   forall dom depth awA awB.
   ( HiddenClockResetEnable dom
   , KnownNat awA
-  , 2 <= awA
   , KnownNat awB
-  , 2 <= awB
   , KnownNat depth
   , 1 <= depth
   ) =>
@@ -154,8 +150,7 @@ wbStorageDP ::
   (Signal dom (WishboneS2M (Bytes 4)), Signal dom (WishboneS2M (Bytes 4)))
 wbStorageDP initial aM2S bM2S = (aS2M, bS2M)
  where
-  storageOut = case lessThanMax @awA @awB @2 of
-    Dict -> wbStorage' @_ @depth @(Max awA awB) initial storageIn
+  storageOut = wbStorage' @_ @depth @(Max awA awB) initial storageIn
 
   storageIn :: Signal dom (WishboneM2S (Max awA awB) 4 (Bytes 4))
   storageIn = mux (nowActive .==. pure A) (resizeM2SAddr <$> aM2S) (resizeM2SAddr <$> bM2S)
@@ -189,7 +184,6 @@ wbStorage ::
   forall dom depth aw.
   ( HiddenClockResetEnable dom
   , KnownNat aw
-  , 2 <= aw
   , KnownNat depth
   , 1 <= depth
   ) =>
@@ -204,7 +198,6 @@ wbStorage' ::
   forall dom depth aw.
   ( HiddenClockResetEnable dom
   , KnownNat aw
-  , 2 <= aw
   , KnownNat depth
   , 1 <= depth
   ) =>
@@ -237,8 +230,8 @@ wbStorage' initContent wbIn = delayControls wbIn wbOut
     , (emptyWishboneS2M @(Bytes 4)){acknowledge, readData = readDataGo, err}
     )
    where
-    (bitCoerce . resize -> wbAddr :: Index depth, alignment) = split @_ @(aw - 2) @2 addr
-    addrLegal = addr < (natToNum @(4 * depth)) && alignment == 0
+    wbAddr = unpack $ resize addr :: Index depth
+    addrLegal = addr < (natToNum @depth)
 
     masterActive = strobe && busCycle
     err = masterActive && not addrLegal
@@ -445,7 +438,6 @@ registerWbC ::
   , KnownNat nBytes
   , 1 <= nBytes
   , KnownNat aw
-  , 2 <= aw
   ) =>
   -- | Determines the write priority on write collisions
   RegisterWritePriority ->
@@ -476,7 +468,6 @@ registerWb ::
   , KnownNat nBytes
   , 1 <= nBytes
   , KnownNat addrW
-  , 2 <= addrW
   ) =>
   -- | Determines the write priority on write collisions
   RegisterWritePriority ->
@@ -510,7 +501,6 @@ registerWbE ::
   , KnownNat nBytes
   , 1 <= nBytes
   , KnownNat addrW
-  , 2 <= addrW
   ) =>
   -- | Determines the write priority on write collisions
   RegisterWritePriority ->
@@ -542,14 +532,12 @@ registerWbE writePriority initVal wbIn sigIn sigByteEnables = (regOut, wbOut)
     , regIn0
     )
    where
-    (alignedAddress, alignment) = split @_ @(addrW - 2) @2 addr
-    addressRange = maxBound :: Index (Max 1 (Regs a (nBytes * 8)))
-    invalidAddress = (alignedAddress > resize (pack addressRange)) || alignment /= 0
+    invalidAddress = addr > resize (pack (maxBound :: Index (Max 1 (Regs a (nBytes * 8)))))
     masterActive = strobe && busCycle
     err = masterActive && invalidAddress
     acknowledge = masterActive && not err
     wbWriting = writeEnable && acknowledge
-    wbAddr = unpack . resize $ pack alignedAddress :: Index (Max 1 (Regs a (nBytes * 8)))
+    wbAddr = unpack (resize addr) :: Index (Max 1 (Regs a (nBytes * 8)))
     readData = case getRegsLe regOut0 of
       RegisterBank vec -> vec !! wbAddr
 

bittide/src/Bittide/Node.hs

@@ -58,7 +58,8 @@ data NodeConfig externalLinks gppes where
     ( KnownNat nmuBusses
     , nmuBusses ~ ((BussesPerGppe * gppes) + 1 + NmuInternalBusses)
     , KnownNat nmuRemBusWidth
-    , nmuRemBusWidth ~ (32 - CLog 2 nmuBusses)
+    , nmuRemBusWidth ~ (30 - CLog 2 nmuBusses)
+    , CLog 2 nmuBusses <= 30
     ) =>
     -- | Configuration for the 'node's 'managementUnit'.
     ManagementConfig ((BussesPerGppe * gppes) + 1) ->
@@ -89,7 +90,7 @@ node (NodeConfig nmuConfig switchConfig gppeConfigs) linksIn = linksOut
     unzip $ gppe <$> zip3 gppeConfigs switchToPes (unconcatI peM2Ss)
 
 type NmuInternalBusses = 6
-type NmuRemBusWidth nodeBusses = 32 - CLog 2 (nodeBusses + NmuInternalBusses)
+type NmuRemBusWidth nodeBusses = 30 - CLog 2 (nodeBusses + NmuInternalBusses)
 
 {- | Configuration for the 'managementUnit' and its 'Bittide.Link'.
 The management unit contains the 4 wishbone busses that each pe has
@@ -127,7 +128,9 @@ The order of Wishbone busses is as follows:
 ('scatterUnitWb' :> 'gatherUnitWb' :> Nil).
 -}
 gppe ::
-  (KnownNat nmuRemBusWidth, 2 <= nmuRemBusWidth, HiddenClockResetEnable dom) =>
+  ( HiddenClockResetEnable dom
+  , KnownNat nmuRemBusWidth
+  ) =>
   -- |
   -- ( Configures all local parameters
   -- , Incoming 'Bittide.Link'

bittide/src/Bittide/ProcessingElement.hs

@@ -32,6 +32,9 @@ data PeConfig nBusses where
     , 1 <= depthI
     , KnownNat depthD
     , 1 <= depthD
+    , KnownNat nBusses
+    , 2 <= nBusses
+    , CLog 2 nBusses <= 30
     ) =>
     -- | The 'MemoryMap' for the contained 'singleMasterInterconnect'.
     MemoryMap nBusses ->
@@ -46,15 +49,11 @@ data PeConfig nBusses where
 -}
 processingElement ::
   forall dom nBusses.
-  ( HiddenClockResetEnable dom
-  , KnownNat nBusses
-  , 2 <= nBusses
-  , CLog 2 nBusses <= 30
-  ) =>
+  (HiddenClockResetEnable dom) =>
   PeConfig nBusses ->
   Circuit
     (Jtag dom)
-    (Vec (nBusses - 2) (Wishbone dom 'Standard (MappedBusAddrWidth 32 nBusses) (Bytes 4)))
+    (Vec (nBusses - 2) (Wishbone dom 'Standard (MappedBusAddrWidth 30 nBusses) (Bytes 4)))
 processingElement (PeConfig memMapConfig initI initD) = circuit $ \jtagIn -> do
   (iBus0, dBus0) <- rvCircuit (pure low) (pure low) (pure low) -< jtagIn
   iBus1 <- ilaWb (SSymbol @"instructionBus") 2 D4096 -< iBus0
@@ -94,25 +93,18 @@ rvCircuit ::
   Signal dom Bit ->
   Circuit
     (Jtag dom)
-    ( Wishbone dom 'Standard 32 (Bytes 4)
-    , Wishbone dom 'Standard 32 (Bytes 4)
+    ( Wishbone dom 'Standard 30 (Bytes 4)
+    , Wishbone dom 'Standard 30 (Bytes 4)
     )
 rvCircuit tInterrupt sInterrupt eInterrupt = Circuit go
  where
-  go (jtagIn, (iBusIn, dBusIn)) = (jtagOut, (iBusOut, dBusOut))
+  go (jtagIn, (iBusIn, dBusIn)) = (jtagOut, (iBusWbM2S <$> cpuOut, dBusWbM2S <$> cpuOut))
    where
     tupToCoreIn (timerInterrupt, softwareInterrupt, externalInterrupt, iBusWbS2M, dBusWbS2M) = CpuIn{..}
     rvIn = tupToCoreIn <$> bundle (tInterrupt, sInterrupt, eInterrupt, iBusIn, dBusIn)
     (cpuOut, jtagOut) = vexRiscv hasClock (hasReset `unsafeOrReset` jtagReset) rvIn jtagIn
     jtagReset = unsafeFromActiveHigh (delay False (bitToBool . debugReset <$> jtagOut))
 
-    -- The VexRiscv instruction- and data-busses assume a conceptual [Bytes 4] memory
-    -- while our storages work like [Bytes 1]. This is also why the address width of
-    -- the VexRiscv busses are 30 bit and still cover the whole address space.
-    -- These shifts bring the addresses "back into the byte domain" so to speak.
-    iBusOut = mapAddr ((`shiftL` 2) . extend @_ @_ @2) . iBusWbM2S <$> cpuOut
-    dBusOut = mapAddr ((`shiftL` 2) . extend) . dBusWbM2S <$> cpuOut
-
 -- | Map a function over the address field of 'WishboneM2S'
 mapAddr ::
   (BitVector aw1 -> BitVector aw2) ->