Set k=2e-9, sample frequency 60 ms

bittide-instances/src/Bittide/Instances/Hitl/IlaPlot.hs

@@ -105,7 +105,7 @@ stamp between the nodes.
 type SyncPulsePeriod = Milliseconds 5
 
 -- | The period of the scheduled capture (must be a multiple of 'SyncPulsePeriod').
-type ScheduledCapturePeriod = Milliseconds 20
+type ScheduledCapturePeriod = Milliseconds 60
 
 {- | An upper bound on the number of synchronized pulses during a test
 run. The bound allows to count pulses up to 5 minutes without

bittide-tools/clockcontrol/plot/Main.hs

@@ -700,8 +700,7 @@ plotTest refDom testDir cfg dir globalOutDir = do
     , dpDrift
     , dpRfStage
     , mapMaybe (uncurry $ liftA2 (,)) $
-        Vec.toList $
-          Vec.zip dpDataCounts dpStability
+        zip (Vec.toList dpDataCounts) (repeat (Just (StabilityIndication False False)))
     )
 
   writeTop (fromMaybe "digraph{}" -> str) =

bittide/src/Bittide/ClockControl/Callisto.hs

@@ -171,7 +171,7 @@ callisto ControlConfig{..} mask scs dataCounts state =
   -- `HwCcTopologies.commonStepSizeSelect`.
   --
   k_p, fStep :: forall d. DSignal dom d Float
-  k_p = pure 2e-8
+  k_p = pure 2e-9
   fStep = pure 10e-9
 
   r_k :: DSignal dom F.FromS32DefDelay Float

firmware-support/bittide-sys/src/callisto.rs

@@ -118,7 +118,7 @@ pub fn callisto(
     // `k_p` (proportional gain) is copied from the Julia implementation. `fStep` should
     // match the step size of the clock boards. For all our HITL tests this is set by
     // `HwCcTopologies.commonStepSizeSelect`.
-    const K_P: f32 = 2e-8;
+    const K_P: f32 = 2e-9;
     const FSTEP: f32 = 10e-9;
 
     let n_buffers = availability_mask.count_ones();