TEST: just use one TX clock

bittide · Sep 5, 2024 · 3e01f86 · 3e01f86
1 parent 1be068e
commit 3e01f86
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/FullMeshSwCc.hs b/bittide-instances/src/Bittide/Instances/Hitl/FullMeshSwCc.hs
@@ -203,7 +203,7 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
   -- Transceiver setup
   gthAllReset = unsafeFromActiveLow spiDone
 
-  transceivers =
+  transceivers0 =
     transceiverPrbsN
       @GthTx
       @GthRx
@@ -225,6 +225,7 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
         , txReadys = txAllStables
         , rxReadys = repeat (pure True)
         }
+  transceivers = transceivers0 {Transceiver.txClocks = repeat (head transceivers0.txClocks)}
   txAllStables = zipWith (xpmCdcSingle sysClk) transceivers.txClocks (repeat allStable1)
   allStable1 = sticky sysClk syncRst allStable0
   txResets2 =