WIP Circuitify Bittide Node

bittide/src/Bittide/Ethernet/Mac.hs

@@ -46,7 +46,6 @@ macStatusInterfaceWb ::
   ( CP.HiddenClockResetEnable dom
   , KnownNat nBytes
   , KnownNat aw
-  , 2 <= aw
   , 1 <= nBytes
   , counterWidth <= nBytes * 8
   ) =>

bittide/src/Bittide/Node.hs

@@ -4,14 +4,16 @@
 {-# LANGUAGE GADTs #-}
 {-# OPTIONS_GHC -fconstraint-solver-iterations=6 #-}
 
+{-# OPTIONS -fplugin=Protocols.Plugin #-}
+
 module Bittide.Node where
 
 import Clash.Prelude
 import Clash.Sized.Vector.ToTuple (vecToTuple)
 
 import Protocols
+import Protocols.Idle
 import Protocols.Wishbone
-
 import VexRiscv
 
 import Bittide.Calendar
@@ -23,6 +25,10 @@ import Bittide.Switch
 
 import Control.Arrow ((&&&))
 
+instance IdleCircuit (Jtag dom) where
+  idleFwd _ = pure $ JtagIn low low low
+  idleBwd _ = pure $ JtagOut low low
+
 {- | A simple node consisting of one external bidirectional link and two 'gppe's.
 This node's 'switch' has a 'CalendarConfig' of for a 'calendar' with up to @1024@ entries,
 however, the 'calendar' is initialized with a single entry of repeated zeroes.
@@ -158,6 +164,25 @@ gppe (GppeConfig scatterConfig gatherConfig peConfig, linkIn, vecToTuple -> (nmu
 
 {-# NOINLINE managementUnit #-}
 
+gppeC ::
+  (KnownNat nmuRemBusWidth, HiddenClockResetEnable dom) =>
+  -- | Configures all local parameters
+  GppeConfig nmuRemBusWidth ->
+  -- |
+  -- ( Incoming 'Bittide.Link'
+  -- , Incoming @Vector@ of master busses
+  -- )
+  Circuit
+    (CSignal dom (DataLink 64), Vec 2 (Wishbone dom 'Standard nmuRemBusWidth (Bytes 4)))
+    (CSignal dom (DataLink 64))
+gppeC (GppeConfig scatterConfig gatherConfig peConfig) = circuit $ \(linkIn, nmuWbs) -> do
+  [wbScatCal, wbGathCal] <- idC -< nmuWbs
+  jtag <- idleSource -< ()
+  [wbScat, wbGu] <- processingElement peConfig -< jtag
+  linkOut <- gatherUnitWbC gatherConfig -< (wbGu, wbGathCal)
+  scatterUnitWbC scatterConfig -< (linkIn, wbScat, wbScatCal)
+  idC -< linkOut
+
 {- | A special purpose 'processingElement' that manages a Bittide Node. It contains
 a 'processingElement', 'linkToPe' and 'peToLink' which create the interface for the
 Bittide Link. It takes a 'ManagementConfig', incoming link and a vector of incoming
@@ -191,3 +216,24 @@ managementUnit (ManagementConfig scatterConfig gatherConfig peConfig) linkIn nod
   (vecToTuple -> (nmuM2S0, nmuM2S1), nodeM2Ss) = splitAtI rest
   (_, nmuM2Ss) = toSignals (processingElement peConfig) (pure $ JtagIn low low low, nmuS2Ms)
   nmuS2Ms = suS2M :> guS2M :> nmuS2M0 :> nmuS2M1 :> nodeS2Ms
+
+managementUnitC ::
+  forall dom nodeBusses .
+  ( HiddenClockResetEnable dom
+  , CLog 2 (nodeBusses + NmuInternalBusses) <= 30) =>
+  -- |
+  -- ( Configures all local parameters
+  -- , Incoming 'Bittide.Link'
+  -- , Incoming @Vector@ of master busses
+  -- )
+  ManagementConfig nodeBusses ->
+  Circuit
+    (CSignal dom (DataLink 64))
+    (CSignal dom (DataLink 64), Vec nodeBusses (Wishbone dom 'Standard (NmuRemBusWidth nodeBusses) (Bytes 4)))
+managementUnitC (ManagementConfig scatterConfig gatherConfig peConfig) = circuit $ \linkIn -> do
+  jtag <- idleSource -< ()
+  peWbs <- processingElement peConfig -< jtag
+  ([wbScatCal, wbScat, wbGathCal, wbGu], nmuWbs) <- splitAtC d4 -< peWbs
+  linkOut <- gatherUnitWbC gatherConfig -< (wbGu, wbGathCal)
+  scatterUnitWbC scatterConfig -< (linkIn, wbScat, wbScatCal)
+  idC -< (linkOut, nmuWbs)

bittide/src/Bittide/ScatterGather.hs

@@ -8,20 +8,25 @@
 
 module Bittide.ScatterGather (
   scatterUnitWb,
+  scatterUnitWbC,
   ScatterConfig (..),
   gatherUnitWb,
+  gatherUnitWbC,
   GatherConfig (..),
 ) where
 
 import Clash.Prelude
 
-import Protocols.Wishbone
-
 import Bittide.Calendar
 import Bittide.DoubleBufferedRam
 import Bittide.Extra.Maybe
 import Bittide.SharedTypes
 
+import Protocols
+import Protocols.Wishbone
+
+import Data.Constraint.Nat.Extra
+
 {- | Existential type to explicitly differentiate between a configuration for
 the 'scatterUnitWb' and 'gatherUnitWb' at type level and hide the memory depth from
 higher level APIs.
@@ -185,26 +190,48 @@ addStalling endOfMetacycle (incomingBus@WishboneS2M{..}, wbAddr, writeOp0) =
 
 {-# NOINLINE scatterUnitWb #-}
 
+scatterUnitWbC ::
+  forall dom awSu nBytesCal awCal.
+  ( HiddenClockResetEnable dom
+  , KnownNat awSu
+  , KnownNat nBytesCal
+  , 1 <= nBytesCal
+  , KnownNat awCal
+  ) =>
+  -- | Configuration for the 'calendar'.
+  ScatterConfig nBytesCal awCal ->
+  Circuit
+    ( CSignal dom (DataLink 64)
+    , Wishbone dom 'Standard awSu (Bytes 4)
+    , Wishbone dom 'Standard awCal (Bytes nBytesCal))
+    ()
+scatterUnitWbC conf = case cancelMulDiv @nBytesCal @8 of
+  Dict -> Circuit go
+   where
+    go ((linkIn, wbM2SSu, wbM2SCal), _) = ((pure (), wbS2MSu, wbS2MCal), ())
+     where
+      (wbS2MSu, wbS2MCal) = scatterUnitWb conf wbM2SCal linkIn wbM2SSu
+
 {- | Wishbone addressable 'scatterUnit', the wishbone port can read the data from this
 memory element as if it has a 32 bit port by selecting the upper 32 or lower 32 bits
 of the read data.
 -}
 scatterUnitWb ::
-  forall dom addrWidthSu nBytesCal addrWidthCal.
+  forall dom awSu nBytesCal awCal.
   ( HiddenClockResetEnable dom
-  , KnownNat addrWidthSu
+  , KnownNat awSu
   , KnownNat nBytesCal
   , 1 <= nBytesCal
-  , KnownNat addrWidthCal
+  , KnownNat awCal
   ) =>
   -- | Configuration for the 'calendar'.
-  ScatterConfig nBytesCal addrWidthCal ->
+  ScatterConfig nBytesCal awCal ->
   -- | Wishbone (master -> slave) port 'calendar'.
-  Signal dom (WishboneM2S addrWidthCal nBytesCal (Bytes nBytesCal)) ->
+  Signal dom (WishboneM2S awCal nBytesCal (Bytes nBytesCal)) ->
   -- | Incoming frame from Bittide link.
   Signal dom (DataLink 64) ->
   -- | Wishbone (master -> slave) port scatter memory.
-  Signal dom (WishboneM2S addrWidthSu 4 (Bytes 4)) ->
+  Signal dom (WishboneM2S awSu 4 (Bytes 4)) ->
   -- |
   -- 1. Wishbone (slave -> master) port scatter memory
   -- 2. Wishbone (slave -> master) port 'calendar'
@@ -226,24 +253,46 @@ scatterUnitWb (ScatterConfig calConfig) wbInCal linkIn wbInSu =
 
 {-# NOINLINE gatherUnitWb #-}
 
+gatherUnitWbC ::
+  forall dom awGu nBytesCal awCal.
+  ( HiddenClockResetEnable dom
+  , KnownNat awGu
+  , KnownNat nBytesCal
+  , 1 <= nBytesCal
+  , KnownNat awCal
+  ) =>
+  -- | Configuration for the 'calendar'.
+  GatherConfig nBytesCal awCal ->
+  Circuit
+    ( Wishbone dom 'Standard awGu (Bytes 4)
+    , Wishbone dom 'Standard awCal (Bytes nBytesCal)
+    )
+    (CSignal dom (DataLink 64))
+gatherUnitWbC conf = case (cancelMulDiv @nBytesCal @8) of
+  Dict -> Circuit go
+   where
+    go ((wbInGu, wbInCal), _) = ((wbOutGu, wbOutCal), linkOut)
+     where
+      (linkOut, wbOutGu, wbOutCal) = gatherUnitWb conf wbInCal wbInGu
+
 {- | Wishbone addressable 'gatherUnit', the wishbone port can write data to this
 memory element as if it has a 32 bit port by controlling the byte enables of the
 'gatherUnit' based on the third bit.
 -}
 gatherUnitWb ::
-  forall dom addrWidthGu nBytesCal addrWidthCal.
+  forall dom awGu nBytesCal awCal.
   ( HiddenClockResetEnable dom
-  , KnownNat addrWidthGu
+  , KnownNat awGu
   , KnownNat nBytesCal
   , 1 <= nBytesCal
-  , KnownNat addrWidthCal
+  , KnownNat awCal
   ) =>
   -- | Configuration for the 'calendar'.
-  GatherConfig nBytesCal addrWidthCal ->
+  GatherConfig nBytesCal awCal ->
   -- | Wishbone (master -> slave) data 'calendar'.
-  Signal dom (WishboneM2S addrWidthCal nBytesCal (Bytes nBytesCal)) ->
+  Signal dom (WishboneM2S awCal nBytesCal (Bytes nBytesCal)) ->
   -- | Wishbone (master -> slave) port gather memory.
-  Signal dom (WishboneM2S addrWidthGu 4 (Bytes 4)) ->
+  Signal dom (WishboneM2S awGu 4 (Bytes 4)) ->
   -- |
   -- 1. Wishbone (slave -> master) port gather memory
   -- 2. Wishbone (slave -> master) port 'calendar'

bittide/src/Bittide/Switch.hs

@@ -35,7 +35,7 @@ switchC ::
   CalendarConfig nBytes addrW (CalendarEntry links) ->
   Circuit
     ( CSignal dom (Vec links (DataLink frameWidth))
-    , Wishbone dom 'Standard addrW (Bytes nBytes)
+    , Wishbone dom 'Standard addrW (Bytes nBytes) -- calendar interface
     )
     (CSignal dom (Vec links (DataLink frameWidth)))
 switchC conf = case (cancelMulDiv @nBytes @8) of