FincFdec test: change the extra clock to use out1 instead of out0

We want to use this extra clock for other things in other tests.
Namely as a better reference clock in the HwCcTopologies test.
But out0 and out0a share their divider and that won't work there.
(out0a is used as GTH reference clock)

bittide-instances/src/Bittide/Instances/Hitl/FincFdec.hs

@@ -94,7 +94,7 @@ goFincFdecTests clk rst clkControlled testSelect miso =
   (_, spiBusy, spiState@(fmap (== Finished) -> siClkLocked), spiOut) =
     withClockResetEnable clk rst enableGen
       $ si539xSpi
-        Si5395J.testConfig6_200_on_0a_10ppb_and_0
+        Si5395J.testConfig6_200_on_0a_10ppb_and_1
         (SNat @(Microseconds 1))
         (pure Nothing)
         miso