WIP externally clocked sync out

bittide · Sep 16, 2024 · fe9b48d · fe9b48d
1 parent a474535
commit fe9b48d
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Showing 3 changed files with 20 additions and 4 deletions.
diff --git a/bittide-instances/data/constraints/fullMeshHwCcTest.xdc b/bittide-instances/data/constraints/fullMeshHwCcTest.xdc
@@ -12,6 +12,7 @@ set_property BOARD_PART_PIN GPIO_LED_0_LS [get_ports spiDone]
 set_clock_groups \
   -asynchronous \
   -group [get_clocks -include_generated_clocks {SYSCLK_300_p}] \
+  -group [get_clocks -include_generated_clocks {USER_SMA_CLOCK_p}]
   -group [get_clocks -include_generated_clocks {SMA_MGT_REFCLK_C_p}]
 
 # Color   | FPGA pin      | LVLSHFT       | Connection
@@ -42,3 +43,7 @@ set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM17} [get_ports {MISO}]
 set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN H27} [get_ports {SYNC_IN}]
 # USER_SMA_GPIO_N (connected on node 0 to SYNC_IN of all nodes)
 set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN G27} [get_ports {SYNC_OUT}]
+
+# USER_SMA_CLOCK
+set_property -dict {IOSTANDARD LVDS PACKAGE_PIN D23} [get_ports {USER_SMA_CLOCK_p}]
+set_property -dict {IOSTANDARD LVDS PACKAGE_PIN C23} [get_ports {USER_SMA_CLOCK_n}]
diff --git a/bittide-instances/src/Bittide/Instances/Domains.hs b/bittide-instances/src/Bittide/Instances/Domains.hs
@@ -25,6 +25,7 @@ createDomain vXilinxSystem{vName="Basic625", vPeriod=hzToPeriod 625e6, vResetKin
 createDomain vXilinxSystem{vName="Ext125", vPeriod= hzToPeriod 125e6, vResetKind=Asynchronous}
 createDomain vXilinxSystem{vName="Ext200", vPeriod=hzToPeriod 200e6, vResetKind=Asynchronous}
 createDomain vXilinxSystem{vName="Ext300", vPeriod=hzToPeriod 300e6, vResetKind=Asynchronous}
+createDomain vXilinxSystem{vName="Ext300A", vPeriod=hzToPeriod 300e6, vResetKind=Asynchronous}
 
 createDomain vXilinxSystem{vName="GthRx", vPeriod=hzToPeriod 125e6}
 createDomain vXilinxSystem{vName="GthTx", vPeriod= hzToPeriod 125e6}

diff --git a/bittide-instances/src/Bittide/Instances/Hitl/HwCcTopologies.hs b/bittide-instances/src/Bittide/Instances/Hitl/HwCcTopologies.hs
@@ -80,6 +80,7 @@ import Clash.Annotations.TH (makeTopEntity)
 import Clash.Class.Counter
 import Clash.Cores.Xilinx.GTH
 import Clash.Cores.Xilinx.Ila (Depth (..), IlaConfig (..), ila, ilaConfig)
+import Clash.Cores.Xilinx.Xpm.Cdc.Single
 import Clash.Sized.Extra (unsignedToSigned)
 import Clash.Xilinx.ClockGen
 
@@ -141,7 +142,7 @@ partsPerToSteps :: PartsPer -> FincFdecCount
 partsPerToSteps =
   fromIntegral . roundFloatInteger . PartsPer.toSteps commonStepSizePartsPer
 
-commonSpiConfig :: TestConfig6_200_on_0a_RegisterMap
+commonSpiConfig :: Si5395RegisterMap
 commonSpiConfig = case commonStepSizeSelect of
   PPB_100 -> testConfig6_200_on_0a_100ppb_and_1
 
@@ -667,11 +668,14 @@ hwCcTopologyWithRiscvTest refClkDiff sysClkDiff syncIn rxns rxps miso =
   testConfig = hitlVio disabled sysClk done success
 
 makeTopEntity 'hwCcTopologyWithRiscvTest
+unsafeResetSynch :: (KnownDomain domIn, KnownDomain domOut) => Reset domIn -> Reset domOut
+unsafeResetSynch = unsafeFromActiveHigh . unsafeSynchronizer clockGen clockGen . unsafeToActiveHigh
 
 -- | Top entity for this test. See module documentation for more information.
 hwCcTopologyTest ::
   "SMA_MGT_REFCLK_C" ::: DiffClock Ext200 ->
   "SYSCLK_300" ::: DiffClock Ext300 ->
+  "USER_SMA_CLOCK" ::: DiffClock Ext300A ->
   "SYNC_IN" ::: Signal Basic125 Bool ->
   "GTH_RX_NS" ::: TransceiverWires GthRxS LinkCount ->
   "GTH_RX_PS" ::: TransceiverWires GthRxS LinkCount ->
@@ -682,21 +686,27 @@ hwCcTopologyTest ::
       ::: ( "FINC" ::: Signal Basic125 Bool
           , "FDEC" ::: Signal Basic125 Bool
           )
-  , "SYNC_OUT" ::: Signal Basic125 Bool
+  , "SYNC_OUT" ::: Signal Basic125A Bool
   , "spiDone" ::: Signal Basic125 Bool
   , ""
       ::: ( "SCLK" ::: Signal Basic125 Bool
           , "MOSI" ::: Signal Basic125 Bit
           , "CSB" ::: Signal Basic125 Bool
           )
   )
-hwCcTopologyTest refClkDiff sysClkDiff syncIn rxns rxps miso =
+hwCcTopologyTest refClkDiff sysClkDiff userSmaClkDiff syncIn rxns rxps miso =
   (txns, txps, unbundle hwFincFdecs, syncOut, spiDone, spiOut)
  where
   refClk = ibufds_gte3 refClkDiff :: Clock Ext200
   (sysClk, sysRst) = clockWizardDifferential sysClkDiff noReset
-  ilaControl@IlaControl{..} = ilaPlotSetup IlaPlotSetup{..}
+  (smaClk :: Clock Basic125A, smaRst :: Reset Basic125A) = clockWizardDifferential userSmaClkDiff (unsafeResetSynch $ unsafeFromActiveLow spiDone)
+  ilaControl@IlaControl{syncRst,syncStart} = ilaPlotSetup IlaPlotSetup{..}
   startTest = isJust <$> testConfig
+  syncOut = dflipflop smaClk
+        $ syncOutGenerator smaClk (sync sysClk smaClk startTest)
+        $ trueFor (SNat @(Seconds 5)) smaClk smaRst (sync sysClk smaClk allReady)
+
+  sync = xpmCdcSingle
 
   cfg = fromMaybe disabled <$> testConfig