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.gitignore
.gitignore
 
 
ALU.vhd
ALU.vhd
 
 
ALUcontrol.vhd
ALUcontrol.vhd
 
 
HDandFUtest.asm
HDandFUtest.asm
 
 
MS.asm
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README.md
README.md
 
 
add_sub.vhd
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and32.vhd
and32.vhd
 
 
controlLogic.vhd
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datapath.vhd
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debughardware.do
debughardware.do
 
 
decodeStage.vhd
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decoder5to32.vhd
decoder5to32.vhd
 
 
dffNbit.vhd
dffNbit.vhd
 
 
dflipflop.vhd
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executionStage.vhd
executionStage.vhd
 
 
fetchStage.vhd
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forwardingUnit.vhd
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fulladder.vhd
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fulladderNbit.vhd
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fulladderNbit_d.vhd
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hardwareScheduledPipeline.vhd
hardwareScheduledPipeline.vhd
 
 
hazardDetection.vhd
hazardDetection.vhd
 
 
ifetchlogic.vhd
ifetchlogic.vhd
 
 
instructMem.vhd
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mem.vhd
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memoryStage.vhd
memoryStage.vhd
 
 
mipsRegister.vhd
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mips_extender.vhd
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mux2to1.vhd
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mux2to15bit.vhd
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mux2to1Nbit.vhd
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mux2to1NbitDataflow.vhd
mux2to1NbitDataflow.vhd
 
 
mux32to1.vhd
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mux4to1.vhd
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mux8to1.vhd
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muxedDff.vhd
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my_and2.vhd
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my_dff.vhd
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my_inv.vhd
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my_or2.vhd
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my_or8.vhd
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my_xor2.vhd
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nor32.vhd
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ones_comp_d.vhd
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ones_comp_s.vhd
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or32.vhd
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pipeEXMEM.vhd
pipeEXMEM.vhd
 
 
pipeIDEX.vhd
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pipeIFID.vhd
pipeIFID.vhd
 
 
pipeMEMWB.vhd
pipeMEMWB.vhd
 
 
pipeline.vhd
pipeline.vhd
 
 
proj3test.do
proj3test.do
 
 
right_shift32.vhd
right_shift32.vhd
 
 
shift32.vhd
shift32.vhd
 
 
simpleMips.vhd
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singleCycle.vhd
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tb_SimplifiedMIPSProcessor.vhd
tb_SimplifiedMIPSProcessor.vhd
 
 
testbenchFinal.asm
testbenchFinal.asm
 
 
xor32.vhd
xor32.vhd
 
 

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CprE 381 - Computer Architecture and Assembly Level Programming

  • Built a single-cycle MIPS processor from scratch in VHDL
  • Revised into a software-scheduled pipelined MIPS processor
  • Finished with a fully-implemented, hardware-scheduled MIPS processor w/ forwarding & hazard detection

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CprE381 - Computer Organization and Assembly Level Programming

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