vhdl2.md

VHDL Overview #2

This lecture will provide a brief overview of process statements in VHDL.

Reading

• Chapter 5 of Chu
  • 5.1 - 5.1.2
  • 5.2 - 5.3
  • 5.4 - 5.4.1
  • 5.5.1
• 8.4 - 8.5 of Chu

Key Concepts

• VHDL Process statement
  • Sesitivity list
• Sequential assignment statements vs variable assignment statement
• If statement
• Case statement
• Inference of basic memory elements in VHDL