This repository contains the lecture schedule (including links to lecture summaries), descriptions of the assignments, and code necessary for completing the assignments for ECEN 520.
| Date | Lecture |
|---|---|
| Week 1 | |
| 9/4/2024 | Class Overview |
| 9/6/2024 | SystemVerilog Review |
| Week 2 | |
| 9/9/2024 | Behavioral SystemVerilog |
| 9/11/2024 | FSM Design |
| 9/13/2024 | |
| Week 3 | |
| 9/16/2024 | FSM Output Glitches and State Encoding |
| 9/18/2024 | RTL Design using ASM Diagrams |
| 9/20/2024 | SystemVerilog Testbenches |
| Week 4 | |
| 9/23/2024 | Functions, Tasks, and Threads |
| 9/25/2024 | SystemVerilog Types |
| 9/27/2024 | Verification with UVM |
| Week 5 | |
| 9/30/2024 | SystemVerilog Types continued - no quiz |
| 10/2/2024 | SPI Controller |
| 10/4/2024 | Exam #1 |
| Week 6 | |
| 10/7/2024 | Memories |
| 10/9/2024 | Timing overview and review |
| 10/11/2024 | Clock Skew |
| Week 7 | |
| 10/14/2024 | Xilinx Clock Timing reports |
| 10/16/2024 | Xilinx Clock Resources (MMCM) |
| 10/18/2024 | Reset timing and strategies |
| Week 8 | |
| 10/21/2024 | Metastability & Synchronizer design |
| 10/23/2024 | Clock domain crossing |
| 10/25/2024 | Handshaking and Data Transfer |
| Week 9 | |
| 10/28/2024 | Poor Design Practice |
| 10/30/2024 | No Class (catch up) |
| 11/1/2024 | Pipelining and Retiming |
| Week 10 | |
| 11/4/2024 | VHDL Part 1 |
| 11/6/2024 | VHDL Part 2 |
| 11/8/2024 | Exam #2 |
| Week 11 | |
| 11/11/2024 | Digital Arithmetic #1 |
| 11/13/2024 | Digital Arithmetic #2 |
| 11/15/2024 | DSP Blocks |
| Week 12 | |
| 11/18/2024 | DDR |
| 11/20/2024 | IO Resources |
| 11/22/2024 | No Class (gone for research) |
| Week 13 | |
| 11/25/2024 | No Class (Gone for research) |
| 11/27/2024 | No Class - Thanksgiving Break |
| 11/29/2024 | No Class - Thanksgiving Break |
| Week 14 | |
| 12/2/2024 | CLB Blocks |
| 12/4/2024 | AXI Bus |
| 12/6/2024 | IP Integrator |
| Week 15 | Alternative HDLs |
| 12/9/2024 | Review for Exam |
| 12/11/2024 | Final Exam in class |
All assignments must be submitted on a classroom GitHub repository. Review the assignment mechanics page to learn how to properly submit your assignments.
| # | Name | Directory/Lab Tag |
|---|---|---|
| 1 | UART Transmitter-Simulation | tx_sim |
| 2 | UART Transmitter-Synthesis and Download | tx_download |
| 3 | UART Receiver Simulation | rx_sim |
| 4 | UART Synthesis and Download | rx_download |
| 5 | SPI Controller-Simulation | spi_cntrl |
| 6 | SPI Controller-Download | spi_download |
| 7 | BRAM | bram |
| 8 | BRAM-Download | bram_download |
| 9 | MMCM Clocking | mmcm |
| 10 | VGA Controller (VHDL) | vga |
| 11 | DDR | ddr |