update to latest library versions, more common structure

Makefile

@@ -54,23 +54,23 @@ SOURCES += src/ub_lib/usb_cdc_lolevel/usbd_usr.c
 CPPFLAGS += -DUSE_STDPERIPH_DRIVER
 #CPPFLAGS += -DUSE_FULL_ASSERT
 
-INCDIRS += lib/inc/peripherals
-INCDIRS += lib/inc
-INCDIRS += lib/inc/core
-
-SOURCES += lib/src/peripherals/stm32f4xx_adc.c
-SOURCES += lib/src/peripherals/stm32f4xx_dma.c
-SOURCES += lib/src/peripherals/stm32f4xx_flash.c
-SOURCES += lib/src/peripherals/stm32f4xx_gpio.c
-SOURCES += lib/src/peripherals/stm32f4xx_pwr.c
-SOURCES += lib/src/peripherals/stm32f4xx_rcc.c
-SOURCES += lib/src/peripherals/stm32f4xx_tim.c
-SOURCES += lib/src/peripherals/stm32f4xx_usart.c
-SOURCES += lib/src/peripherals/misc.c
-
-SOURCES += lib/startup_stm32f4xx.s
-
-#CPPFLAGS += -DSTM32F40_41xxx
+INCDIRS += lib/STM32F4xx_StdPeriph_Driver-V1.6.0/inc
+INCDIRS += lib/CMSIS/Include
+INCDIRS += lib/CMSIS/Device/ST/STM32F4xx/Include
+
+SOURCES += lib/STM32F4xx_StdPeriph_Driver-V1.6.0/src/stm32f4xx_adc.c
+SOURCES += lib/STM32F4xx_StdPeriph_Driver-V1.6.0/src/stm32f4xx_dma.c
+SOURCES += lib/STM32F4xx_StdPeriph_Driver-V1.6.0/src/stm32f4xx_flash.c
+SOURCES += lib/STM32F4xx_StdPeriph_Driver-V1.6.0/src/stm32f4xx_gpio.c
+SOURCES += lib/STM32F4xx_StdPeriph_Driver-V1.6.0/src/stm32f4xx_pwr.c
+SOURCES += lib/STM32F4xx_StdPeriph_Driver-V1.6.0/src/stm32f4xx_rcc.c
+SOURCES += lib/STM32F4xx_StdPeriph_Driver-V1.6.0/src/stm32f4xx_tim.c
+SOURCES += lib/STM32F4xx_StdPeriph_Driver-V1.6.0/src/stm32f4xx_usart.c
+SOURCES += lib/STM32F4xx_StdPeriph_Driver-V1.6.0/src/misc.c
+
+SOURCES += lib/CMSIS/Device/ST/STM32F4xx/Source/startup_stm32f40_41xxx.s
+
+CPPFLAGS += -DSTM32F40_41xxx
 LDSCRIPT = stm32_flash.ld
 
 #============================================================================
@@ -224,7 +224,7 @@ clean:
 	rm -rf $(OBJDIR)
 	@$(MAKE) -f bootloader/Makefile clean
 	@$(MAKE) -f stm32f103/Makefile clean
-	
+
 # Include the base rules
 #
 include base.mak

bootloader/Makefile

@@ -28,23 +28,20 @@ SOURCES += shared/crc32.c
 CPPFLAGS += -DUSE_STDPERIPH_DRIVER
 #CPPFLAGS += -DUSE_FULL_ASSERT
 
-INCDIRS += lib/inc/peripherals
-INCDIRS += lib/inc
-INCDIRS += lib/inc/core
-
-SOURCES += lib/src/peripherals/stm32f4xx_adc.c
-SOURCES += lib/src/peripherals/stm32f4xx_dma.c
-SOURCES += lib/src/peripherals/stm32f4xx_flash.c
-SOURCES += lib/src/peripherals/stm32f4xx_gpio.c
-SOURCES += lib/src/peripherals/stm32f4xx_pwr.c
-SOURCES += lib/src/peripherals/stm32f4xx_rcc.c
-SOURCES += lib/src/peripherals/stm32f4xx_tim.c
-SOURCES += lib/src/peripherals/stm32f4xx_usart.c
-SOURCES += lib/src/peripherals/misc.c
-
-SOURCES += lib/startup_stm32f4xx.s
-
-#CPPFLAGS += -DSTM32F40_41xxx
+INCDIRS += lib/STM32F4xx_StdPeriph_Driver-V1.6.0/inc
+INCDIRS += lib/CMSIS/Include
+INCDIRS += lib/CMSIS/Device/ST/STM32F4xx/Include
+
+SOURCES += lib/STM32F4xx_StdPeriph_Driver-V1.6.0/src/stm32f4xx_flash.c
+SOURCES += lib/STM32F4xx_StdPeriph_Driver-V1.6.0/src/stm32f4xx_gpio.c
+SOURCES += lib/STM32F4xx_StdPeriph_Driver-V1.6.0/src/stm32f4xx_pwr.c
+SOURCES += lib/STM32F4xx_StdPeriph_Driver-V1.6.0/src/stm32f4xx_rcc.c
+SOURCES += lib/STM32F4xx_StdPeriph_Driver-V1.6.0/src/stm32f4xx_usart.c
+SOURCES += lib/STM32F4xx_StdPeriph_Driver-V1.6.0/src/misc.c
+
+SOURCES += lib/CMSIS/Device/ST/STM32F4xx/Source/startup_stm32f40_41xxx.s
+
+CPPFLAGS += -DSTM32F40_41xxx
 LDSCRIPT = bootloader/stm32_flash.ld
 
 #============================================================================
@@ -175,7 +172,7 @@ flash: build showsize
 clean:
 	@echo Cleaning project:
 	rm -rf $(OBJDIR)
-	
+
 # Include the base rules
 #
 include base.mak

bootloader/src/system_stm32f4xx.c

@@ -303,8 +303,7 @@ void SystemCoreClockUpdate(void)
     case 0x04:  /* HSE used as system clock source */
       SystemCoreClock = HSE_VALUE;
       break;
-    case 0x08:  /* PLL used as system clock source */
-
+    case 0x08:  /* PLL P used as system clock source */
       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
          SYSCLK = PLL_VCO / PLL_P
          */
@@ -374,7 +373,7 @@ static void SetSysClock(void)
   {
     /* Enable high performance mode, System frequency up to 168 MHz */
     RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-    PWR->CR |= PWR_CR_PMODE;
+    PWR->CR |= PWR_CR_VOS;
 
     /* HCLK = SYSCLK / 1*/
     RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
@@ -398,7 +397,7 @@ static void SetSysClock(void)
     }
 
     /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
-    FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
 
     /* Select the main PLL as system clock source */
     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));