ensure that @external memories are std_mem_d1 (#1605)

calyxir · Jul 16, 2023 · 2137cf0 · 2137cf0
1 parent 267b0d1
commit 2137cf0
Showing 1 changed file with 12 additions and 4 deletions.
diff --git a/src/backend/xilinx/toplevel.rs b/src/backend/xilinx/toplevel.rs
@@ -93,14 +93,22 @@ impl Backend for XilinxInterfaceBackend {
     }
 }
 
-fn external_memories_cells(
-    comp: &ir::Component,
-) -> Vec<calyx_ir::RRC<ir::Cell>> {
+fn external_memories_cells(comp: &ir::Component) -> Vec<ir::RRC<ir::Cell>> {
     comp.cells
         .iter()
         // find external memories
         .filter(|cell_ref| {
-            cell_ref.borrow().attributes.has(ir::BoolAttr::External)
+            let cell = cell_ref.borrow();
+            // NOTE(rachit): We only support one dimensional std_mem_d1 memories
+            if cell.attributes.has(ir::BoolAttr::External) {
+                if !cell.is_primitive(Some("std_mem_d1")) {
+                    panic!("cell `{}' marked with `@external' but is not a std_mem_d1. The AXI generator currently only supports `std_mem_d1'", cell.name())
+                } else {
+                   true
+                }
+            } else {
+                false
+            }
         })
         .cloned()
         .collect()