[Cider 2.0] Remaining comb prims and the seq mem implementation (#1967)

* Get the low hanging combinational prims * Remove the dead_code thingy * all hail clippy * revamp the shape construct * seq mem support
calyxir · Mar 11, 2024 · 23cd0a1 · 23cd0a1
1 parent bdbddcb
commit 23cd0a1
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Showing 15 changed files with 417 additions and 366 deletions.
diff --git a/interp/src/errors.rs b/interp/src/errors.rs
@@ -176,6 +176,10 @@ pub enum InterpreterError {
     //TODO Griffin: Make this more descriptive
     #[error("Attempted to write an undefined memory address")]
     UndefinedWriteAddr,
+
+    // TODO Griffin: Make this more descriptive
+    #[error("Attempted to read an undefined memory address")]
+    UndefinedReadAddr,
 }
 
 impl InterpreterError {

diff --git a/interp/src/flatten/flat_ir/base.rs b/interp/src/flatten/flat_ir/base.rs
@@ -172,7 +172,7 @@ impl From<GlobalPortIdx> for GlobalPortRef {
 
 impl GlobalPortRef {
     #[must_use]
-    pub fn as_port(&self) -> Option<&GlobalPortIdx> {
+    pub fn _as_port(&self) -> Option<&GlobalPortIdx> {
         if let Self::Port(v) = self {
             Some(v)
         } else {
@@ -181,7 +181,7 @@ impl GlobalPortRef {
     }
 
     #[must_use]
-    pub fn as_ref(&self) -> Option<&GlobalRefPortIdx> {
+    pub fn _as_ref(&self) -> Option<&GlobalRefPortIdx> {
         if let Self::Ref(v) = self {
             Some(v)
         } else {

diff --git a/interp/src/flatten/flat_ir/control/structures.rs b/interp/src/flatten/flat_ir/control/structures.rs
@@ -241,21 +241,3 @@ pub(crate) enum ContainmentType {
     /// A ref cell/port
     Ref,
 }
-
-impl ContainmentType {
-    /// Returns `true` if the containment type is [`Local`].
-    ///
-    /// [`Local`]: ContainmentType::Local
-    #[must_use]
-    pub(crate) fn is_local(&self) -> bool {
-        matches!(self, Self::Local)
-    }
-
-    /// Returns `true` if the containment type is [`Ref`].
-    ///
-    /// [`Ref`]: ContainmentType::Ref
-    #[must_use]
-    pub(crate) fn is_ref(&self) -> bool {
-        matches!(self, Self::Ref)
-    }
-}
diff --git a/interp/src/flatten/flat_ir/control/translator.rs b/interp/src/flatten/flat_ir/control/translator.rs
@@ -309,7 +309,6 @@ fn insert_cell(
 pub struct Layout {
     port_map: PortMapper,
     cell_map: CellMapper,
-    component_map: ComponentMapper,
 }
 
 fn compute_local_layout(

diff --git a/interp/src/flatten/primitives/builder.rs b/interp/src/flatten/primitives/builder.rs
@@ -44,7 +44,7 @@ pub fn build_primitive(
             PrimType1::Le => Box::new(StdLe::new(base_port)),
             PrimType1::Lsh => Box::new(StdLsh::new(base_port, *width)),
             PrimType1::Rsh => Box::new(StdRsh::new(base_port, *width)),
-            PrimType1::Mux => Box::new(StdMux::new(base_port, *width)),
+            PrimType1::Mux => Box::new(StdMux::new(base_port)),
             PrimType1::Wire => Box::new(StdWire::new(base_port)),
             PrimType1::SignedAdd => Box::new(StdAdd::new(base_port)),
             PrimType1::SignedSub => Box::new(StdSub::new(base_port)),
@@ -87,26 +87,38 @@ pub fn build_primitive(
             frac_width: _,
         } => todo!(),
         CellPrototype::Slice {
-            in_width: _,
-            out_width: _,
-        } => todo!(),
+            in_width: _, // Not actually needed, should probably remove
+            out_width,
+        } => Box::new(StdSlice::new(base_port, *out_width)),
         CellPrototype::Pad {
-            in_width: _,
-            out_width: _,
-        } => todo!(),
+            in_width: _, // Not actually needed, should probably remove
+            out_width,
+        } => Box::new(StdPad::new(base_port, *out_width)),
         CellPrototype::Cat {
+            // Turns out under the assumption that the primitive is well formed,
+            // none of these parameter values are actually needed
             left: _,
             right: _,
             out: _,
-        } => todo!(),
+        } => Box::new(StdCat::new(base_port)),
         CellPrototype::MemD1 {
             mem_type,
             width,
             size,
             idx_size: _,
         } => match mem_type {
-            MemType::Seq => todo!("SeqMem primitives are not currently defined in the flat interpreter"),
-            MemType::Std => Box::new(CombMemD1::new(base_port, *width, false, *size as usize))
+            MemType::Seq => Box::new(SeqMemD1::new(
+                base_port,
+                *width,
+                false,
+                *size as usize,
+            )),
+            MemType::Std => Box::new(CombMemD1::new(
+                base_port,
+                *width,
+                false,
+                *size as usize,
+            )),
         },
         CellPrototype::MemD2 {
             mem_type,
@@ -116,8 +128,18 @@ pub fn build_primitive(
             d0_idx_size: _,
             d1_idx_size: _,
         } => match mem_type {
-            MemType::Seq => todo!("SeqMem primitives are not currently defined in the flat interpreter"),
-            MemType::Std => Box::new(CombMemD2::new(base_port, *width, false, (*d0_size as usize, *d1_size as usize))),
+            MemType::Seq => Box::new(SeqMemD2::new(
+                base_port,
+                *width,
+                false,
+                (*d0_size as usize, *d1_size as usize),
+            )),
+            MemType::Std => Box::new(CombMemD2::new(
+                base_port,
+                *width,
+                false,
+                (*d0_size as usize, *d1_size as usize),
+            )),
         },
         CellPrototype::MemD3 {
             mem_type,
@@ -128,9 +150,19 @@ pub fn build_primitive(
             d0_idx_size: _,
             d1_idx_size: _,
             d2_idx_size: _,
-        }  => match mem_type {
-            MemType::Seq => todo!("SeqMem primitives are not currently defined in the flat interpreter"),
-            MemType::Std => Box::new(CombMemD3::new(base_port, *width, false, (*d0_size as usize, *d1_size as usize, *d2_size as usize))),
+        } => match mem_type {
+            MemType::Seq => Box::new(SeqMemD3::new(
+                base_port,
+                *width,
+                false,
+                (*d0_size as usize, *d1_size as usize, *d2_size as usize),
+            )),
+            MemType::Std => Box::new(CombMemD3::new(
+                base_port,
+                *width,
+                false,
+                (*d0_size as usize, *d1_size as usize, *d2_size as usize),
+            )),
         },
         CellPrototype::MemD4 {
             mem_type,
@@ -143,9 +175,29 @@ pub fn build_primitive(
             d1_idx_size: _,
             d2_idx_size: _,
             d3_idx_size: _,
-        }=> match mem_type {
-            MemType::Seq => todo!("SeqMem primitives are not currently defined in the flat interpreter"),
-            MemType::Std => Box::new(CombMemD4::new(base_port, *width, false, (*d0_size as usize, *d1_size as usize, *d2_size as usize, *d3_size as usize))),
+        } => match mem_type {
+            MemType::Seq => Box::new(SeqMemD4::new(
+                base_port,
+                *width,
+                false,
+                (
+                    *d0_size as usize,
+                    *d1_size as usize,
+                    *d2_size as usize,
+                    *d3_size as usize,
+                ),
+            )),
+            MemType::Std => Box::new(CombMemD4::new(
+                base_port,
+                *width,
+                false,
+                (
+                    *d0_size as usize,
+                    *d1_size as usize,
+                    *d2_size as usize,
+                    *d3_size as usize,
+                ),
+            )),
         },
         CellPrototype::Unknown(_, _) => todo!(),
     }

diff --git a/interp/src/flatten/primitives/combinational.rs b/interp/src/flatten/primitives/combinational.rs
@@ -53,13 +53,12 @@ impl Primitive for StdConst {
 
 pub struct StdMux {
     base: GlobalPortIdx,
-    width: u32,
 }
 
 impl StdMux {
     declare_ports![ COND: 0, TRU: 1, FAL:2, OUT: 3];
-    pub fn new(base: GlobalPortIdx, width: u32) -> Self {
-        Self { base, width }
+    pub fn new(base: GlobalPortIdx) -> Self {
+        Self { base }
     }
 }
 
@@ -504,6 +503,12 @@ comb_primitive!(StdPad[OUT_WIDTH](input [0]) -> (out [1]) {
     Ok( Some(input.ext(OUT_WIDTH as usize)))
 });
 
+comb_primitive!(StdCat(left [0], right [1]) -> (out [2]) {
+    all_defined!(left, right);
+
+    Ok(Some(Value::concat(left, right)))
+});
+
 // ===================== Unsynthesizeable Operations ======================
 comb_primitive!(StdUnsynMult[WIDTH](left [0], right [1]) -> (out [2]) {
     all_defined!(left, right);

diff --git a/interp/src/flatten/primitives/macros.rs b/interp/src/flatten/primitives/macros.rs
@@ -19,7 +19,7 @@ macro_rules! make_getters {
         $(
             #[inline]
             fn $port(&self) -> $crate::flatten::flat_ir::prelude::GlobalPortIdx {
-                ($crate::flatten::structures::index_trait::IndexRef::index(&self.$base) + $offset).into()
+                ($crate::flatten::structures::index_trait::IndexRef::index(&self.$base) + &self.addresser.non_address_base() + $offset).into()
             }
         )+