getting data for systolic arrays

benchmarks/large_polybench/linear-algebra-trmm.fuse

@@ -5,6 +5,9 @@
 
 
 
+
+
+
 // END macro definition
 
 decl alpha_int: ubit<32>[1];
@@ -13,10 +16,10 @@ decl B_int: ubit<32>[60][80];
 
 for (let i: ubit<6> = 0..60) {
   for (let j: ubit<7> = 0..80) {
-    let k: ubit<6> = i + 1;
+    let k: ubit<6> = i + (1 as ubit<6>);
     // XXX: Try rewriting this as a 'for' loop
     while (k < 60) {
-      decor "#pragma HLS loop_tripcount min=0 max=7 avg=4"
+      decor "#pragma HLS loop_tripcount WHILE0"
       let B_i_j: ubit<32> = B_int[i][j];
       ---
       let B_k_j: ubit<32> = B_int[k][j];

benchmarks/small_polybench/linear-algebra-trmm.fuse

@@ -5,6 +5,7 @@
 
 
 
+
 // END macro definition
 
 decl alpha_int: ubit<32>[1];
@@ -13,10 +14,10 @@ decl B_int: ubit<32>[8][12];
 
 for (let i: ubit<4> = 0..8) {
   for (let j: ubit<4> = 0..12) {
-    let k: ubit<4> = i + 1;
+    let k: ubit<4> = i + (1 as ubit<4>);
     // XXX: Try rewriting this as a 'for' loop
     while (k < 8) {
-      decor "#pragma HLS loop_tripcount min=0 max=7 avg=4"
+      decor "#pragma HLS loop_tripcount WHILE0"
       let B_i_j: ubit<32> = B_int[i][j];
       ---
       let B_k_j: ubit<32> = B_int[k][j];

bin/gen_data.py

@@ -26,14 +26,20 @@ def modulate_size(size, banks):
     else:
         return [0]
 
-def main(path):
+def replace(mapping, key):
+    if type(key) == int:
+        return key
+    else:
+        return mapping[key]
+
+def main(path, all_random):
     template = json.load(path.open())
     mapping = template['key']
     memory = template['memory']
     result = {}
     for key in memory:
-        size = [mapping[key] for key in memory[key]['data']]
-        banks = memory[key]['banks']
+        size = [replace(mapping, key) for key in memory[key]['data']]
+        banks = [replace(mapping, key) for key in memory[key]['banks']]
         variants = [""] # include empty string so that we have the empty variant
         if 'variants' in memory[key]:
             variants += memory[key]['variants']
@@ -42,13 +48,19 @@ def main(path):
         for var in variants:
             # result[f'{key}{var}'] = data # include unbanked for Dahlia
             for b in generate_bank_strings(banks):
-                result[f'{key}{var}{b}'] = data
+                if all_random:
+                    result[f'{key}{var}{b}'] = generate(modulate_size(size, banks), bitwidth)
+                else:
+                    result[f'{key}{var}{b}'] = data
     print(json.dumps(result, indent=2))
 
 if __name__ == "__main__":
     filename = Path(sys.argv[1])
+    all_random = False
+    if len(sys.argv) > 2:
+        all_random = True
     if filename.exists():
-        main(filename)
+        main(filename, all_random)
     else:
         print(f"{filename} doesn't exist.")
         exit(1)

bin/run-benchmark

@@ -32,7 +32,7 @@ $script_dir/json_to_dat.py --mode json --output "$meminit" "$data"
 
 $script_dir/find-dahlia $input --lower -b futil -l error > "$benchmark"
 
-$script_dir/../target/debug/futil "$benchmark" -b verilog --verilator -d static-timing -l $script_dir/.. \
+$script_dir/../target/debug/futil "$benchmark" -b verilog --verilator -l $script_dir/.. \
     | DATA="$meminit" $script_dir/gen-vcd - 2> "$tmp/log" > "$tmp/out.vcd"
 
 # Translate the outputs back to a JSON filetmp

runt.toml

@@ -134,6 +134,5 @@ name = "(systolic array) simulation"
 paths = [ "systolic-lang/tests/verilog/*.expect" ]
 cmd = """
 DATA=./systolic-lang/tests/data ./bin/gen-vcd {} 2>/dev/null | vcdump | jq -f {}.jq
-
 """
 expect_dir = "systolic-lang/tests/simulation/"

systolic-lang/hls_gemm/gemm2.fuse

@@ -0,0 +1,50 @@
+// BEGIN macro defintions
+
+
+
+
+
+// END macro definitions
+decl C_int: ubit<32>[2][2];
+decl A_int: ubit<32>[2][2];
+decl B_int: ubit<32>[2][2];
+
+let C: ubit<32>[2 bank 2][2 bank 2];
+let A: ubit<32>[2 bank 2][2];
+let B: ubit<32>[2][2 bank 2];
+
+view C_sh = C[_: bank 1][_: bank 1];
+view A_sh = A[_: bank 1][_: bank 1];
+view B_sh = B[_: bank 1][_: bank 1];
+
+// Input interface.
+for (let i: ubit<4> = 0..2) {
+  for (let j: ubit<4> = 0..2) {
+    A_sh[i][j] := A_int[i][j];
+    B_sh[i][j] := B_int[i][j];
+    C_sh[i][j] := C_int[i][j];
+  }
+}
+
+---
+for (let i: ubit<4> = 0..2) unroll 2 {
+  // Loop order has to change since j is not defined in the combine
+  // block otherwise.
+  for (let j: ubit<4> = 0..2) unroll 2 {
+    for (let k: ubit<4> = 0..2) {
+      let v: ubit<32> = A[i][k] * B[k][j];
+    } combine {
+      C[i][j] += v;
+    }
+  }
+}
+
+---
+
+// Output interface.
+
+for (let i: ubit<4> = 0..2) {
+  for (let j: ubit<4> = 0..2) {
+    C_int[i][j] := C_sh[i][j];
+  }
+}

systolic-lang/hls_gemm/gemm2.header

@@ -0,0 +1,7 @@
+// BEGIN macro defintions
+
+define(N, 2)
+define(N_ur, 2)
+define(N_bw, ubit<4>)
+
+// END macro definitions

systolic-lang/hls_gemm/gemm3.fuse

@@ -0,0 +1,50 @@
+// BEGIN macro defintions
+
+
+
+
+
+// END macro definitions
+decl C_int: ubit<32>[3][3];
+decl A_int: ubit<32>[3][3];
+decl B_int: ubit<32>[3][3];
+
+let C: ubit<32>[3 bank 3][3 bank 3];
+let A: ubit<32>[3 bank 3][3];
+let B: ubit<32>[3][3 bank 3];
+
+view C_sh = C[_: bank 1][_: bank 1];
+view A_sh = A[_: bank 1][_: bank 1];
+view B_sh = B[_: bank 1][_: bank 1];
+
+// Input interface.
+for (let i: ubit<4> = 0..3) {
+  for (let j: ubit<4> = 0..3) {
+    A_sh[i][j] := A_int[i][j];
+    B_sh[i][j] := B_int[i][j];
+    C_sh[i][j] := C_int[i][j];
+  }
+}
+
+---
+for (let i: ubit<4> = 0..3) unroll 3 {
+  // Loop order has to change since j is not defined in the combine
+  // block otherwise.
+  for (let j: ubit<4> = 0..3) unroll 3 {
+    for (let k: ubit<4> = 0..3) {
+      let v: ubit<32> = A[i][k] * B[k][j];
+    } combine {
+      C[i][j] += v;
+    }
+  }
+}
+
+---
+
+// Output interface.
+
+for (let i: ubit<4> = 0..3) {
+  for (let j: ubit<4> = 0..3) {
+    C_int[i][j] := C_sh[i][j];
+  }
+}

systolic-lang/hls_gemm/gemm3.header

@@ -0,0 +1,7 @@
+// BEGIN macro defintions
+
+define(N, 3)
+define(N_ur, 3)
+define(N_bw, ubit<4>)
+
+// END macro definitions

systolic-lang/hls_gemm/gemm4.fuse

@@ -0,0 +1,50 @@
+// BEGIN macro defintions
+
+
+
+
+
+// END macro definitions
+decl C_int: ubit<32>[4][4];
+decl A_int: ubit<32>[4][4];
+decl B_int: ubit<32>[4][4];
+
+let C: ubit<32>[4 bank 4][4 bank 4];
+let A: ubit<32>[4 bank 4][4];
+let B: ubit<32>[4][4 bank 4];
+
+view C_sh = C[_: bank 1][_: bank 1];
+view A_sh = A[_: bank 1][_: bank 1];
+view B_sh = B[_: bank 1][_: bank 1];
+
+// Input interface.
+for (let i: ubit<4> = 0..4) {
+  for (let j: ubit<4> = 0..4) {
+    A_sh[i][j] := A_int[i][j];
+    B_sh[i][j] := B_int[i][j];
+    C_sh[i][j] := C_int[i][j];
+  }
+}
+
+---
+for (let i: ubit<4> = 0..4) unroll 4 {
+  // Loop order has to change since j is not defined in the combine
+  // block otherwise.
+  for (let j: ubit<4> = 0..4) unroll 4 {
+    for (let k: ubit<4> = 0..4) {
+      let v: ubit<32> = A[i][k] * B[k][j];
+    } combine {
+      C[i][j] += v;
+    }
+  }
+}
+
+---
+
+// Output interface.
+
+for (let i: ubit<4> = 0..4) {
+  for (let j: ubit<4> = 0..4) {
+    C_int[i][j] := C_sh[i][j];
+  }
+}

systolic-lang/hls_gemm/gemm4.header

@@ -0,0 +1,7 @@
+// BEGIN macro defintions
+
+define(N, 4)
+define(N_ur, 4)
+define(N_bw, ubit<4>)
+
+// END macro definitions

systolic-lang/hls_gemm/gemm6.fuse

@@ -0,0 +1,50 @@
+// BEGIN macro defintions
+
+
+
+
+
+// END macro definitions
+decl C_int: ubit<32>[6][6];
+decl A_int: ubit<32>[6][6];
+decl B_int: ubit<32>[6][6];
+
+let C: ubit<32>[6 bank 6][6 bank 6];
+let A: ubit<32>[6 bank 6][6];
+let B: ubit<32>[6][6 bank 6];
+
+view C_sh = C[_: bank 1][_: bank 1];
+view A_sh = A[_: bank 1][_: bank 1];
+view B_sh = B[_: bank 1][_: bank 1];
+
+// Input interface.
+for (let i: ubit<4> = 0..6) {
+  for (let j: ubit<4> = 0..6) {
+    A_sh[i][j] := A_int[i][j];
+    B_sh[i][j] := B_int[i][j];
+    C_sh[i][j] := C_int[i][j];
+  }
+}
+
+---
+for (let i: ubit<4> = 0..6) unroll 6 {
+  // Loop order has to change since j is not defined in the combine
+  // block otherwise.
+  for (let j: ubit<4> = 0..6) unroll 6 {
+    for (let k: ubit<4> = 0..6) {
+      let v: ubit<32> = A[i][k] * B[k][j];
+    } combine {
+      C[i][j] += v;
+    }
+  }
+}
+
+---
+
+// Output interface.
+
+for (let i: ubit<4> = 0..6) {
+  for (let j: ubit<4> = 0..6) {
+    C_int[i][j] := C_sh[i][j];
+  }
+}

systolic-lang/hls_gemm/gemm6.header

@@ -0,0 +1,7 @@
+// BEGIN macro defintions
+
+define(N, 6)
+define(N_ur, 6)
+define(N_bw, ubit<4>)
+
+// END macro definitions

systolic-lang/hls_gemm/gemm8.fuse

@@ -0,0 +1,50 @@
+// BEGIN macro defintions
+
+
+
+
+
+// END macro definitions
+decl C_int: ubit<32>[8][8];
+decl A_int: ubit<32>[8][8];
+decl B_int: ubit<32>[8][8];
+
+let C: ubit<32>[8 bank 8][8 bank 8];
+let A: ubit<32>[8 bank 8][8];
+let B: ubit<32>[8][8 bank 8];
+
+view C_sh = C[_: bank 1][_: bank 1];
+view A_sh = A[_: bank 1][_: bank 1];
+view B_sh = B[_: bank 1][_: bank 1];
+
+// Input interface.
+for (let i: ubit<4> = 0..8) {
+  for (let j: ubit<4> = 0..8) {
+    A_sh[i][j] := A_int[i][j];
+    B_sh[i][j] := B_int[i][j];
+    C_sh[i][j] := C_int[i][j];
+  }
+}
+
+---
+for (let i: ubit<4> = 0..8) unroll 8 {
+  // Loop order has to change since j is not defined in the combine
+  // block otherwise.
+  for (let j: ubit<4> = 0..8) unroll 8 {
+    for (let k: ubit<4> = 0..8) {
+      let v: ubit<32> = A[i][k] * B[k][j];
+    } combine {
+      C[i][j] += v;
+    }
+  }
+}
+
+---
+
+// Output interface.
+
+for (let i: ubit<4> = 0..8) {
+  for (let j: ubit<4> = 0..8) {
+    C_int[i][j] := C_sh[i][j];
+  }
+}