Prefer seq_mems to comb_mems all over (#2127)

* Port Python code to seq mems

* Update expect files to deal with new seq mems

* Fix gen_exp to use seq mems

* Catch up expect files to seq mems

* Trigger Build

* Silly mistake

* Expect files chasing after silly mistake

calyx-py/calyx/gen_exp.py

@@ -704,9 +704,9 @@ def build_base_not_e(degree, width, int_width, is_signed) -> Program:
     main = builder.component("main")
     base_reg = main.reg(width, "base_reg")
     exp_reg = main.reg(width, "exp_reg")
-    x = main.comb_mem_d1("x", width, 1, 1, is_external=True)
-    b = main.comb_mem_d1("b", width, 1, 1, is_external=True)
-    ret = main.comb_mem_d1("ret", width, 1, 1, is_external=True)
+    x = main.seq_mem_d1("x", width, 1, 1, is_external=True)
+    b = main.seq_mem_d1("b", width, 1, 1, is_external=True)
+    ret = main.seq_mem_d1("ret", width, 1, 1, is_external=True)
     f = main.comp_instance("f", "fp_pow_full")
 
     read_base = main.mem_load_d1(b, 0, base_reg, "read_base")
@@ -740,14 +740,15 @@ def build_base_is_e(degree, width, int_width, is_signed) -> Program:
     main = builder.component("main")
 
     t = main.reg(width, "t")
-    x = main.comb_mem_d1("x", width, 1, 1, is_external=True)
-    ret = main.comb_mem_d1("ret", width, 1, 1, is_external=True)
+    x = main.seq_mem_d1("x", width, 1, 1, is_external=True)
+    ret = main.seq_mem_d1("ret", width, 1, 1, is_external=True)
     e = main.comp_instance("e", "exp")
 
     with main.group("init") as init:
         x.addr0 = 0
-        t.in_ = x.read_data
-        t.write_en = 1
+        x.content_en = 1
+        t.in_ = x.done @ x.read_data
+        t.write_en = x.done @ 1
         init.done = t.done
 
     write_to_memory = main.mem_store_d1(ret, 0, e.out, "write_to_memory")

frontends/ntt-pipeline/gen-ntt-pipeline.py

@@ -206,13 +206,15 @@ def preamble_group(comp: cb.ComponentBuilder, row):
         phis = comp.get_cell("phis")
         with main.group(f"preamble_{row}_reg") as preamble_reg:
             input.addr0 = row
-            reg.write_en = 1
-            reg.in_ = input.read_data
+            input.content_en = 1
+            reg.write_en = input.done @ 1
+            reg.in_ = input.done @ input.read_data
             preamble_reg.done = reg.done
         with main.group(f"preamble_{row}_phi") as preamble_phi:
             phis.addr0 = row
-            phi.write_en = 1
-            phi.in_ = phis.read_data
+            phis.content_en = 1
+            phi.write_en = phis.done @ 1
+            phi.in_ = phis.done @ phis.read_data
             preamble_phi.done = phi.done
 
     def epilogue_group(comp: cb.ComponentBuilder, row):
@@ -222,8 +224,8 @@ def epilogue_group(comp: cb.ComponentBuilder, row):
 
     def insert_cells(comp: cb.ComponentBuilder):
         # memories
-        comp.comb_mem_d1("a", input_bitwidth, n, bitwidth, is_external=True)
-        comp.comb_mem_d1("phis", input_bitwidth, n, bitwidth, is_external=True)
+        comp.seq_mem_d1("a", input_bitwidth, n, bitwidth, is_external=True)
+        comp.seq_mem_d1("phis", input_bitwidth, n, bitwidth, is_external=True)
 
         for r in range(n):
             comp.reg(input_bitwidth, f"r{r}")  # r_regs

tests/correctness/exp/any-base-1.expect

@@ -1,5 +1,5 @@
 {
-  "cycles": 212,
+  "cycles": 216,
   "memories": {
     "b": [
       "4.5"

tests/correctness/exp/any-base-2.expect

@@ -1,5 +1,5 @@
 {
-  "cycles": 207,
+  "cycles": 211,
   "memories": {
     "b": [
       "7.5"

tests/correctness/exp/any-base-3.expect

@@ -1,5 +1,5 @@
 {
-  "cycles": 303,
+  "cycles": 307,
   "memories": {
     "b": [
       "0.75"

tests/correctness/exp/degree-4-signed.expect

@@ -1,5 +1,5 @@
 {
-  "cycles": 55,
+  "cycles": 56,
   "memories": {
     "ret": [
       "2.7182769775390625"

tests/correctness/exp/degree-4-unsigned.expect

@@ -1,5 +1,5 @@
 {
-  "cycles": 48,
+  "cycles": 49,
   "memories": {
     "ret": [
       "2.7182769775390625"

tests/correctness/exp/degree-8-signed.expect

@@ -1,5 +1,5 @@
 {
-  "cycles": 133,
+  "cycles": 134,
   "memories": {
     "ret": [
       "0.0001068115234375"

tests/correctness/exp/degree-8-unsigned.expect

@@ -1,5 +1,5 @@
 {
-  "cycles": 74,
+  "cycles": 75,
   "memories": {
     "ret": [
       "9181.710357666015625"

tests/correctness/exp/neg-base.expect

@@ -1,5 +1,5 @@
 {
-  "cycles": 220,
+  "cycles": 224,
   "memories": {
     "b": [
       "-2.600006103515625"

tests/correctness/ntt-pipeline/ntt-16-reduced-4.expect

@@ -1,5 +1,5 @@
 {
-  "cycles": 647,
+  "cycles": 695,
   "memories": {
     "a": [
       7371,

tests/correctness/ntt-pipeline/ntt-16.expect

@@ -1,5 +1,5 @@
 {
-  "cycles": 200,
+  "cycles": 248,
   "memories": {
     "a": [
       7371,

tests/correctness/ntt-pipeline/ntt-8.expect

@@ -1,5 +1,5 @@
 {
-  "cycles": 142,
+  "cycles": 166,
   "memories": {
     "a": [
       5390,

tests/frontend/exp/degree-2-unsigned.expect

@@ -1,6 +1,6 @@
 import "primitives/core.futil";
 import "primitives/binary_operators.futil";
-import "primitives/memories/comb.futil";
+import "primitives/memories/seq.futil";
 component exp(x: 32) -> (out: 32) {
   cells {
     exponent_value = std_reg(32);
@@ -165,22 +165,24 @@ component fp_pow(base: 32, integer_exp: 32) -> (out: 32) {
 component main() -> () {
   cells {
     t = std_reg(32);
-    @external x = comb_mem_d1(32, 1, 1);
-    @external ret = comb_mem_d1(32, 1, 1);
+    @external x = seq_mem_d1(32, 1, 1);
+    @external ret = seq_mem_d1(32, 1, 1);
     e = exp();
   }
   wires {
     group init {
       x.addr0 = 1'd0;
-      t.in = x.read_data;
-      t.write_en = 1'd1;
+      x.content_en = 1'd1;
+      t.in = x.done ? x.read_data;
+      t.write_en = x.done ? 1'd1;
       init[done] = t.done;
     }
     group write_to_memory {
       ret.addr0 = 1'd0;
       ret.write_en = 1'd1;
       ret.write_data = e.out;
       write_to_memory[done] = ret.done;
+      ret.content_en = 1'd1;
     }
   }
   control {

tests/frontend/exp/degree-4-signed.expect

@@ -1,6 +1,6 @@
 import "primitives/core.futil";
 import "primitives/binary_operators.futil";
-import "primitives/memories/comb.futil";
+import "primitives/memories/seq.futil";
 component exp(x: 16) -> (out: 16) {
   cells {
     exponent_value = std_reg(16);
@@ -258,22 +258,24 @@ component fp_pow(base: 16, integer_exp: 16) -> (out: 16) {
 component main() -> () {
   cells {
     t = std_reg(16);
-    @external x = comb_mem_d1(16, 1, 1);
-    @external ret = comb_mem_d1(16, 1, 1);
+    @external x = seq_mem_d1(16, 1, 1);
+    @external ret = seq_mem_d1(16, 1, 1);
     e = exp();
   }
   wires {
     group init {
       x.addr0 = 1'd0;
-      t.in = x.read_data;
-      t.write_en = 1'd1;
+      x.content_en = 1'd1;
+      t.in = x.done ? x.read_data;
+      t.write_en = x.done ? 1'd1;
       init[done] = t.done;
     }
     group write_to_memory {
       ret.addr0 = 1'd0;
       ret.write_en = 1'd1;
       ret.write_data = e.out;
       write_to_memory[done] = ret.done;
+      ret.content_en = 1'd1;
     }
   }
   control {

tests/frontend/exp/degree-4-unsigned.expect

@@ -1,6 +1,6 @@
 import "primitives/core.futil";
 import "primitives/binary_operators.futil";
-import "primitives/memories/comb.futil";
+import "primitives/memories/seq.futil";
 component exp(x: 16) -> (out: 16) {
   cells {
     exponent_value = std_reg(16);
@@ -229,22 +229,24 @@ component fp_pow(base: 16, integer_exp: 16) -> (out: 16) {
 component main() -> () {
   cells {
     t = std_reg(16);
-    @external x = comb_mem_d1(16, 1, 1);
-    @external ret = comb_mem_d1(16, 1, 1);
+    @external x = seq_mem_d1(16, 1, 1);
+    @external ret = seq_mem_d1(16, 1, 1);
     e = exp();
   }
   wires {
     group init {
       x.addr0 = 1'd0;
-      t.in = x.read_data;
-      t.write_en = 1'd1;
+      x.content_en = 1'd1;
+      t.in = x.done ? x.read_data;
+      t.write_en = x.done ? 1'd1;
       init[done] = t.done;
     }
     group write_to_memory {
       ret.addr0 = 1'd0;
       ret.write_en = 1'd1;
       ret.write_data = e.out;
       write_to_memory[done] = ret.done;
+      ret.content_en = 1'd1;
     }
   }
   control {

tests/frontend/ntt-pipeline/ntt-4-reduced-2.expect

@@ -7,12 +7,12 @@
 // | 3 | a[1] - a[3] * phis[1] | a[2] - a[3] * phis[3] |
 // +---+-----------------------+-----------------------+
 import "primitives/core.futil";
-import "primitives/memories/comb.futil";
+import "primitives/memories/seq.futil";
 import "primitives/binary_operators.futil";
 component main() -> () {
   cells {
-    @external a = comb_mem_d1(32, 4, 3);
-    @external phis = comb_mem_d1(32, 4, 3);
+    @external a = seq_mem_d1(32, 4, 3);
+    @external phis = seq_mem_d1(32, 4, 3);
     r0 = std_reg(32);
     A0 = std_reg(32);
     phi0 = std_reg(32);
@@ -41,50 +41,58 @@ component main() -> () {
   wires {
     group preamble_0_reg {
       a.addr0 = 3'd0;
-      r0.write_en = 1'd1;
-      r0.in = a.read_data;
+      a.content_en = 1'd1;
+      r0.write_en = a.done ? 1'd1;
+      r0.in = a.done ? a.read_data;
       preamble_0_reg[done] = r0.done;
     }
     group preamble_0_phi {
       phis.addr0 = 3'd0;
-      phi0.write_en = 1'd1;
-      phi0.in = phis.read_data;
+      phis.content_en = 1'd1;
+      phi0.write_en = phis.done ? 1'd1;
+      phi0.in = phis.done ? phis.read_data;
       preamble_0_phi[done] = phi0.done;
     }
     group preamble_1_reg {
       a.addr0 = 3'd1;
-      r1.write_en = 1'd1;
-      r1.in = a.read_data;
+      a.content_en = 1'd1;
+      r1.write_en = a.done ? 1'd1;
+      r1.in = a.done ? a.read_data;
       preamble_1_reg[done] = r1.done;
     }
     group preamble_1_phi {
       phis.addr0 = 3'd1;
-      phi1.write_en = 1'd1;
-      phi1.in = phis.read_data;
+      phis.content_en = 1'd1;
+      phi1.write_en = phis.done ? 1'd1;
+      phi1.in = phis.done ? phis.read_data;
       preamble_1_phi[done] = phi1.done;
     }
     group preamble_2_reg {
       a.addr0 = 3'd2;
-      r2.write_en = 1'd1;
-      r2.in = a.read_data;
+      a.content_en = 1'd1;
+      r2.write_en = a.done ? 1'd1;
+      r2.in = a.done ? a.read_data;
       preamble_2_reg[done] = r2.done;
     }
     group preamble_2_phi {
       phis.addr0 = 3'd2;
-      phi2.write_en = 1'd1;
-      phi2.in = phis.read_data;
+      phis.content_en = 1'd1;
+      phi2.write_en = phis.done ? 1'd1;
+      phi2.in = phis.done ? phis.read_data;
       preamble_2_phi[done] = phi2.done;
     }
     group preamble_3_reg {
       a.addr0 = 3'd3;
-      r3.write_en = 1'd1;
-      r3.in = a.read_data;
+      a.content_en = 1'd1;
+      r3.write_en = a.done ? 1'd1;
+      r3.in = a.done ? a.read_data;
       preamble_3_reg[done] = r3.done;
     }
     group preamble_3_phi {
       phis.addr0 = 3'd3;
-      phi3.write_en = 1'd1;
-      phi3.in = phis.read_data;
+      phis.content_en = 1'd1;
+      phi3.write_en = phis.done ? 1'd1;
+      phi3.in = phis.done ? phis.read_data;
       preamble_3_phi[done] = phi3.done;
     }
     group precursor_0 {
@@ -216,24 +224,28 @@ component main() -> () {
       a.write_en = 1'd1;
       a.write_data = A0.out;
       epilogue_0[done] = a.done;
+      a.content_en = 1'd1;
     }
     group epilogue_1 {
       a.addr0 = 3'd1;
       a.write_en = 1'd1;
       a.write_data = A1.out;
       epilogue_1[done] = a.done;
+      a.content_en = 1'd1;
     }
     group epilogue_2 {
       a.addr0 = 3'd2;
       a.write_en = 1'd1;
       a.write_data = A2.out;
       epilogue_2[done] = a.done;
+      a.content_en = 1'd1;
     }
     group epilogue_3 {
       a.addr0 = 3'd3;
       a.write_en = 1'd1;
       a.write_data = A3.out;
       epilogue_3[done] = a.done;
+      a.content_en = 1'd1;
     }
   }
   control {