4 cycles floating point adder by inserting dummy registers; update th…

…e test case and use *.data to input values

primitives/float/addFN.futil

@@ -4,13 +4,17 @@ extern "addFN.sv" {
     sigWidth, 
     numWidth
   ](
+    @clk clk: 1,
+    @reset reset: 1,
+    val: 1,
     control: 1,
     subOp: 1,
     a: numWidth,
     b: numWidth,
     roundingMode: 3
   ) -> (
     out: numWidth,
-    exceptionFlags: 5
+    exceptionFlags: 5,
+    done: 1
   );
 }

primitives/float/addFN.sv

@@ -5,19 +5,22 @@
 `include "primitives/float/source/addRecFN.v"
 `include "primitives/float/source/recFNToFN.v"
 
-module addFN #(parameter expWidth = 3, parameter sigWidth = 3) (
+module addFN #(parameter expWidth = 3, parameter sigWidth = 3, parameter numWidth = 6) (
+    input clk,
+    input reset,
+    input val,
     input [(`floatControlWidth - 1):0] control,
     input subOp,
     input [(expWidth + sigWidth - 1):0] a,
     input [(expWidth + sigWidth - 1):0] b,
     input [2:0] roundingMode,
-    output [(expWidth + sigWidth - 1):0] out,
-    output [4:0] exceptionFlags
+    output logic [(expWidth + sigWidth - 1):0] out,
+    output logic [4:0] exceptionFlags,
+    output done
 );
 
     // Intermediate signals for recoded formats
     wire [(expWidth + sigWidth):0] a_recoded, b_recoded;
-    wire [(expWidth + sigWidth):0] result_recoded;
 
     // Convert 'a' and 'b' from standard to recoded format
     fNToRecFN #(expWidth, sigWidth) convert_a(
@@ -30,23 +33,64 @@ module addFN #(parameter expWidth = 3, parameter sigWidth = 3) (
         .out(b_recoded)
     );
 
+    // Intermediate signals after the adder
+    wire [(expWidth + sigWidth):0] res_recoded;
+    wire [4:0] except_flag;
+
     // Compute recoded numbers
     addRecFN #(expWidth, sigWidth) adder(
         .control(control),
         .subOp(subOp),
         .a(a_recoded),
         .b(b_recoded),
         .roundingMode(roundingMode),
-        .out(result_recoded),
-        .exceptionFlags(exceptionFlags)
+        .out(res_recoded),
+        .exceptionFlags(except_flag)
     );
 
+    wire [(expWidth + sigWidth - 1):0] res_std;
+
     // Convert the result back to standard format
     recFNToFN #(expWidth, sigWidth) convert_res(
-        .in_(result_recoded),
-        .out(out)
+        .in_(res_recoded),
+        .out(res_std)
     );
 
+    // Dummy registers for storing results before output
+    reg [(expWidth + sigWidth - 1):0] out_regs[0:1];
+    reg [4:0] except_flag_regs[0:1];
+
+    always_ff @(posedge clk) begin
+        if (reset) begin
+            out_regs[0] <= 0;
+            out_regs[1] <= 0;
+            except_flag_regs[0] <= 0;
+            except_flag_regs[1] <= 0;
+        end else begin
+            // out
+            out_regs[0] <= res_std;
+            out_regs[1] <= out_regs[0];
+            out <= out_regs[1];
+            // exceptionFlags
+            except_flag_regs[0] <= except_flag;
+            except_flag_regs[1] <= except_flag_regs[0];
+            exceptionFlags <= except_flag_regs[1];
+        end
+    end
+
+    // 4-bit shift register for valid signal
+    reg [3:0] valid_shift_reg = 4'b0000; 
+
+    always @(posedge clk) begin
+    if (reset) begin
+        valid_shift_reg <= 4'b0000;
+    end else begin
+        valid_shift_reg <= {valid_shift_reg[2:0], val};
+    end
+    end
+
+    assign done = valid_shift_reg[3];
+
 endmodule
 
 

tests/correctness/float/addFN.futil

@@ -4,26 +4,36 @@ import "primitives/float/addFN.futil";
 
 component main(@go go: 1) -> (@done done: 1) {
     cells {
-        @external mem = comb_mem_d1(32, 1, 1);
+        @external mem_read_a = comb_mem_d1(32, 1, 1);
+        @external mem_read_b = comb_mem_d1(32, 1, 1);
+        @external mem_write = comb_mem_d1(32, 1, 1);
         addFN0 = addFN(8, 24, 32);
     }
 
     wires {
         group add_std_format {
-            addFN0.a = 32'b01000000100001100110011001100110; // = 4.2
-            addFN0.b = 32'b01000000011000000000000000000000; // = 3.5
+            mem_read_a.addr0 = 1'b0;
+            addFN0.a = mem_read_a.read_data;
+
+            mem_read_b.addr0 = 1'b0;
+            addFN0.b = mem_read_b.read_data;
+
+            addFN0.val = 1'b1;
 
             addFN0.control = 1'b0;
             addFN0.roundingMode = 3'b0;
 
-            mem.addr0 = 1'b0;
-            mem.write_data = addFN0.out;
-            mem.write_en = 1'd1;
-            add_std_format[done] = mem.done;
+            mem_write.addr0 = 1'b0;
+            mem_write.write_data = addFN0.out;
+            mem_write.write_en = 1'b1;
+
+            add_std_format[done] = (mem_write.done & addFN0.done) ? 1'd1;
         }
     }
 
     control {
-        add_std_format;
+        seq {
+            add_std_format;
+        }
     }
 }

tests/correctness/float/addFN.futil.data

@@ -1,8 +1,24 @@
 {
-  "mem": {
+  "mem_read_a": {
+    "data": [1082549862],
+    "format": {
+      "numeric_type": "float_point",
+      "is_signed": false,
+      "width": 32
+    }
+  },
+  "mem_read_b": {
+    "data": [1080033280],
+    "format": {
+      "numeric_type": "float_point",
+      "is_signed": false,
+      "width": 32
+    }
+  },
+  "mem_write": {
     "data": [0],
     "format": {
-      "numeric_type": "floatpoint",
+      "numeric_type": "float_point",
       "is_signed": false,
       "width": 32
     }