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[Cider2] Fixed point data initialization and serialization (#2232)
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EclecticGriffin authored Jul 29, 2024
1 parent b55a062 commit 87f887b
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Showing 8 changed files with 334 additions and 100 deletions.
19 changes: 10 additions & 9 deletions Cargo.lock

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6 changes: 3 additions & 3 deletions interp/src/flatten/structures/environment/env.rs
Original file line number Diff line number Diff line change
Expand Up @@ -1892,15 +1892,15 @@ impl<C: AsRef<Context> + Clone> Simulator<C> {
} else {
MemoryDeclaration::new_bitnum(
name,
*width as usize,
*width,
dims.as_serializing_dim(),
false,
)
}
} else {
MemoryDeclaration::new_bitnum(
name,
*width as usize,
*width,
dims.as_serializing_dim(),
false,
)
Expand All @@ -1921,7 +1921,7 @@ impl<C: AsRef<Context> + Clone> Simulator<C> {
if dump_registers {
dump.push_reg(
name,
*width as usize,
*width,
self.env.cells[cell_index]
.unwrap_primitive()
.dump_memory_state()
Expand Down
2 changes: 1 addition & 1 deletion interp/src/flatten/structures/indexed_map.rs
Original file line number Diff line number Diff line change
Expand Up @@ -143,7 +143,7 @@ where
Self::new()
}
}

#[allow(dead_code)]
pub struct IndexedMapRangeIterator<'range, 'data, K, D>
where
K: IndexRef + PartialOrd,
Expand Down
28 changes: 14 additions & 14 deletions interp/src/serialization/data_dump.rs
Original file line number Diff line number Diff line change
Expand Up @@ -48,12 +48,12 @@ impl From<(usize, usize, usize, usize)> for Dimensions {
pub enum FormatInfo {
Bitnum {
signed: bool,
width: usize,
width: u32,
},
Fixed {
signed: bool,
int_width: usize,
frac_width: usize,
int_width: u32,
frac_width: u32,
},
}

Expand All @@ -65,7 +65,7 @@ impl FormatInfo {
}
}

pub fn width(&self) -> usize {
pub fn width(&self) -> u32 {
match self {
FormatInfo::Bitnum { width, .. } => *width,
FormatInfo::Fixed {
Expand All @@ -87,7 +87,7 @@ pub struct MemoryDeclaration {
impl MemoryDeclaration {
pub fn new_bitnum(
name: String,
width: usize,
width: u32,
dimensions: Dimensions,
signed: bool,
) -> Self {
Expand All @@ -102,8 +102,8 @@ impl MemoryDeclaration {
name: String,
dimensions: Dimensions,
signed: bool,
int_width: usize,
frac_width: usize,
int_width: u32,
frac_width: u32,
) -> Self {
assert!(int_width + frac_width > 0, "width must be greater than 0");

Expand Down Expand Up @@ -135,10 +135,10 @@ impl MemoryDeclaration {
}

pub fn byte_count(&self) -> usize {
self.format.width().div_ceil(8) * self.dimensions.size()
self.format.width().div_ceil(8) as usize * self.dimensions.size()
}

pub fn width(&self) -> usize {
pub fn width(&self) -> u32 {
self.format.width()
}

Expand Down Expand Up @@ -208,7 +208,7 @@ impl DataDump {
pub fn push_reg<T: IntoIterator<Item = u8>>(
&mut self,
name: String,
width: usize,
width: u32,
data: T,
) {
let declaration = MemoryDeclaration::new_bitnum(
Expand Down Expand Up @@ -389,7 +389,7 @@ mod tests {
use proptest::prelude::*;

prop_compose! {
fn arb_memory_declaration()(name in any::<String>(), signed in any::<bool>(), width in 1_usize..=256, size in 1_usize..=500) -> MemoryDeclaration {
fn arb_memory_declaration()(name in any::<String>(), signed in any::<bool>(), width in 1_u32..=256, size in 1_usize..=500) -> MemoryDeclaration {
MemoryDeclaration::new_bitnum(name.to_string(), width, Dimensions::D1(size), signed)
}
}
Expand Down Expand Up @@ -429,7 +429,7 @@ mod tests {
// produced from the memory primitive to not match the one
// serialized into it in the first place
for mem in &header.memories {
let bytes_per_val = mem.width().div_ceil(8);
let bytes_per_val = mem.width().div_ceil(8) as usize;
let rem = mem.width() % 8;
let mask = if rem != 0 { 255u8 >> (8 - rem) } else { 255_u8 };

Expand Down Expand Up @@ -475,7 +475,7 @@ mod tests {
#[test]
fn comb_roundtrip(dump in arb_data_dump()) {
for mem in &dump.header.memories {
let memory_prim = CombMemD1::new_with_init(GlobalPortIdx::new(0), mem.width() as u32, false, mem.size(), dump.get_data(&mem.name).unwrap());
let memory_prim = CombMemD1::new_with_init(GlobalPortIdx::new(0), mem.width(), false, mem.size(), dump.get_data(&mem.name).unwrap());
let data = memory_prim.dump_data();
prop_assert_eq!(dump.get_data(&mem.name).unwrap(), data);
}
Expand All @@ -484,7 +484,7 @@ mod tests {
#[test]
fn seq_roundtrip(dump in arb_data_dump()) {
for mem in &dump.header.memories {
let memory_prim = SeqMemD1::new_with_init(GlobalPortIdx::new(0), mem.width() as u32, false, mem.size(), dump.get_data(&mem.name).unwrap());
let memory_prim = SeqMemD1::new_with_init(GlobalPortIdx::new(0), mem.width(), false, mem.size(), dump.get_data(&mem.name).unwrap());
let data = memory_prim.dump_data();
prop_assert_eq!(dump.get_data(&mem.name).unwrap(), data);
}
Expand Down
2 changes: 2 additions & 0 deletions tools/cider-data-converter/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,8 @@ itertools = { workspace = true }
argh = { workspace = true }
thiserror = "1.0.59"
num-bigint = { version = "0.4.6" }
num-rational = { version = "0.4.2" }
num-traits = { version = "0.2.19" }

[dev-dependencies]
proptest = "1.0.0"
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