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Add compile-repeat
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@ayakayorihiro
ayakayorihiro committed Sep 17, 2024
1 parent 6270ba9 commit 9c2a9a3
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4 changes: 2 additions & 2 deletions tools/profiler/run-up-to-tdcc.sh
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Expand Up @@ -12,13 +12,13 @@ CALYX_DIR=$( dirname $( dirname ${SCRIPT_DIR} ) )
if [ "$2" == "-o" ]; then
(
cd ${CALYX_DIR}
cargo run $1 -p well-formed -p papercut -p canonicalize -p infer-data-path -p collapse-control -p compile-sync-without-sync-reg -p group2seq -p dead-assign-removal -p group2invoke -p infer-share -p inline -p comb-prop -p dead-cell-removal -p cell-share -p simplify-with-control -p compile-invoke -p static-inference -p static-promotion -p compile-repeat -p dead-group-removal -p collapse-control -p static-inline -p merge-assigns -p dead-group-removal -p simplify-static-guards -p add-guard -p static-fsm-opts -p compile-static -p dead-group-removal -p tdcc
cargo run $1 -p compile-repeat -p well-formed -p papercut -p canonicalize -p infer-data-path -p collapse-control -p compile-sync-without-sync-reg -p group2seq -p dead-assign-removal -p group2invoke -p infer-share -p inline -p comb-prop -p dead-cell-removal -p cell-share -p simplify-with-control -p compile-invoke -p static-inference -p static-promotion -p compile-repeat -p dead-group-removal -p collapse-control -p static-inline -p merge-assigns -p dead-group-removal -p simplify-static-guards -p add-guard -p static-fsm-opts -p compile-static -p dead-group-removal -p tdcc
)
else

(
cd ${CALYX_DIR}
cargo run $1 -p well-formed -p papercut -p canonicalize -p compile-sync -p simplify-with-control -p compile-invoke -p static-inline -p merge-assigns -p dead-group-removal -p simplify-static-guards -p add-guard -p static-fsm-opts -p compile-static -p dead-group-removal -p tdcc
cargo run $1 -p compile-repeat -p well-formed -p papercut -p canonicalize -p compile-sync -p simplify-with-control -p compile-invoke -p static-inline -p merge-assigns -p dead-group-removal -p simplify-static-guards -p add-guard -p static-fsm-opts -p compile-static -p dead-group-removal -p tdcc
)

fi
137 changes: 137 additions & 0 deletions tools/profiler/sequentialized-benchmarks/fast6inc.futil
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extern "/home/ayaka/.calyx/primitives/memories/comb.sv" {
primitive comb_mem_d1[WIDTH, SIZE, IDX_SIZE](@read_together addr0: IDX_SIZE, @write_together @data write_data: WIDTH, @write_together @interval @go write_en: 1, @clk clk: 1, @reset reset: 1) -> (@read_together read_data: WIDTH, @done done: 1);
primitive comb_mem_d2[WIDTH, D0_SIZE, D1_SIZE, D0_IDX_SIZE, D1_IDX_SIZE](@read_together @write_together(2) addr0: D0_IDX_SIZE, @read_together @write_together(2) addr1: D1_IDX_SIZE, @write_together @data write_data: WIDTH, @write_together @interval @go write_en: 1, @clk clk: 1, @reset reset: 1) -> (@read_together read_data: WIDTH, @done done: 1);
primitive comb_mem_d3[WIDTH, D0_SIZE, D1_SIZE, D2_SIZE, D0_IDX_SIZE, D1_IDX_SIZE, D2_IDX_SIZE](@read_together @write_together(2) addr0: D0_IDX_SIZE, @read_together @write_together(2) addr1: D1_IDX_SIZE, @read_together @write_together(2) addr2: D2_IDX_SIZE, @write_together @data write_data: WIDTH, @write_together @interval @go write_en: 1, @clk clk: 1, @reset reset: 1) -> (@read_together read_data: WIDTH, @done done: 1);
primitive comb_mem_d4[WIDTH, D0_SIZE, D1_SIZE, D2_SIZE, D3_SIZE, D0_IDX_SIZE, D1_IDX_SIZE, D2_IDX_SIZE, D3_IDX_SIZE](@read_together @write_together(2) addr0: D0_IDX_SIZE, @read_together @write_together(2) addr1: D1_IDX_SIZE, @read_together @write_together(2) addr2: D2_IDX_SIZE, @read_together @write_together(2) addr3: D3_IDX_SIZE, @write_together @data write_data: WIDTH, @write_together @interval @go write_en: 1, @clk clk: 1) -> (@read_together read_data: WIDTH, @done done: 1);
}
extern "/home/ayaka/.calyx/primitives/core.sv" {
comb primitive std_slice<"share"=1>[IN_WIDTH, OUT_WIDTH](@data in: IN_WIDTH) -> (out: OUT_WIDTH);
comb primitive std_pad<"share"=1>[IN_WIDTH, OUT_WIDTH](@data in: IN_WIDTH) -> (out: OUT_WIDTH);
comb primitive std_cat<"share"=1>[LEFT_WIDTH, RIGHT_WIDTH, OUT_WIDTH](@data left: LEFT_WIDTH, @data right: RIGHT_WIDTH) -> (out: OUT_WIDTH);
comb primitive std_bit_slice<"share"=1>[IN_WIDTH, START_IDX, END_IDX, OUT_WIDTH](@data in: IN_WIDTH) -> (out: OUT_WIDTH);
comb primitive std_not<"share"=1>[WIDTH](@data in: WIDTH) -> (out: WIDTH);
comb primitive std_and<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
comb primitive std_or<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
comb primitive std_xor<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
comb primitive std_sub<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
comb primitive std_gt<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
comb primitive std_lt<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
comb primitive std_eq<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
comb primitive std_neq<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
comb primitive std_ge<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
comb primitive std_le<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: 1);
comb primitive std_rsh<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH);
comb primitive std_mux<"share"=1>[WIDTH](@data cond: 1, @data tru: WIDTH, @data fal: WIDTH) -> (out: WIDTH);
}
primitive undef<"share"=1>[WIDTH]() -> (out: WIDTH) {
assign out = 'x;
}
comb primitive std_const<"share"=1>[WIDTH, VALUE]() -> (out: WIDTH) {
assign out = VALUE;
}
comb primitive std_wire<"share"=1>[WIDTH](@data in: WIDTH) -> (out: WIDTH) {
assign out = in;
}
comb primitive std_add<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH) {
assign out = left + right;
}
comb primitive std_lsh<"share"=1>[WIDTH](@data left: WIDTH, @data right: WIDTH) -> (out: WIDTH) {
assign out = left << right;
}
primitive std_reg<"state_share"=1>[WIDTH](@write_together @data in: WIDTH, @write_together @interval @go write_en: 1, @clk clk: 1, @reset reset: 1) -> (@stable out: WIDTH, @done done: 1) {
always_ff @(posedge clk) begin
if (reset) begin
out <= 0;
done <= 0;
end else if (write_en) begin
out <= in;
done <= 1'd1;
end else done <= 1'd0;
end
}
primitive init_one_reg<"state_share"=1>[WIDTH](@write_together @data in: WIDTH, @write_together @interval @go write_en: 1, @clk clk: 1, @reset reset: 1) -> (@stable out: WIDTH, @done done: 1) {
always_ff @(posedge clk) begin
if (reset) begin
out <= 1;
done <= 0;
end else if (write_en) begin
out <= in;
done <= 1'd1;
end else done <= 1'd0;
end
}
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
cells {
@external m = comb_mem_d1(32, 1, 32);
i0 = std_reg(32);
add = std_add(32);
@generated fsm = std_reg(1);
@generated adder = std_add(1);
@generated adder0 = std_add(1);
@generated ud = undef(1);
@generated ud0 = undef(1);
@generated signal_reg = std_reg(1);
}
wires {
group dyn_inc {
add.left = i0.out;
add.right = 32'd1;
i0.in = add.out;
i0.write_en = 1'd1;
dyn_inc[done] = i0.done;
}
group write {
m.write_data = i0.out;
m.write_en = 1'd1;
write[done] = m.done;
}
group early_reset_init {
i0.in = 32'd0;
i0.write_en = 1'd1;
adder.left = fsm.out;
adder.right = 1'd1;
fsm.write_en = 1'd1;
fsm.in = !(fsm.out == 1'd0) ? adder.out;
fsm.in = fsm.out == 1'd0 ? 1'd0;
early_reset_init[done] = ud.out;
}
group early_reset_static_inc {
add.left = i0.out;
add.right = 32'd1;
i0.in = add.out;
i0.write_en = 1'd1;
adder0.left = fsm.out;
adder0.right = 1'd1;
fsm.write_en = 1'd1;
fsm.in = !(fsm.out == 1'd0) ? adder0.out;
fsm.in = fsm.out == 1'd0 ? 1'd0;
early_reset_static_inc[done] = ud0.out;
}
group wrapper_early_reset_init {
early_reset_init[go] = 1'd1;
signal_reg.write_en = fsm.out == 1'd0 & !signal_reg.out ? 1'd1;
signal_reg.in = fsm.out == 1'd0 & !signal_reg.out ? 1'd1;
wrapper_early_reset_init[done] = fsm.out == 1'd0 & signal_reg.out ? 1'd1;
}
group wrapper_early_reset_static_inc {
early_reset_static_inc[go] = 1'd1;
signal_reg.write_en = fsm.out == 1'd0 & !signal_reg.out ? 1'd1;
signal_reg.in = fsm.out == 1'd0 & !signal_reg.out ? 1'd1;
wrapper_early_reset_static_inc[done] = fsm.out == 1'd0 & signal_reg.out ? 1'd1;
}
signal_reg.write_en = fsm.out == 1'd0 & signal_reg.out ? 1'd1;
signal_reg.in = fsm.out == 1'd0 & signal_reg.out ? 1'd0;
}
control {
seq {
wrapper_early_reset_init;
dyn_inc;
wrapper_early_reset_static_inc;
dyn_inc;
wrapper_early_reset_static_inc;
dyn_inc;
wrapper_early_reset_static_inc;
write;
}
}
}
12 changes: 12 additions & 0 deletions tools/profiler/sequentialized-benchmarks/fast6inc.futil.data
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{
"m": {
"data": [
0
],
"format": {
"numeric_type": "bitnum",
"is_signed": false,
"width": 32
}
}
}

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