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modify tests
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@calebmkim
calebmkim committed Jul 15, 2024
1 parent f590f8a commit bd85537
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Showing 5 changed files with 56 additions and 56 deletions.
26 changes: 13 additions & 13 deletions tests/passes/compile-static-interface/compile-static-interface-repeat.expect
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Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,8 @@ static<6> component do_add(left: 32, right: 32, @go go: 1, @clk clk: 1, @reset r
r = std_reg(32);
@generated fsm = std_reg(2);
@generated fsm0 = std_reg(3);
@generated adder = std_add(3);
@generated adder0 = std_add(2);
@generated adder = std_add(2);
@generated adder0 = std_add(3);
@generated ud = undef(1);
@generated ud0 = undef(1);
}
Expand All @@ -19,11 +19,11 @@ static<6> component do_add(left: 32, right: 32, @go go: 1, @clk clk: 1, @reset r
r.in = go & fsm.out == 2'd0 ? add.out;
early_reset_a[go] = fsm.out == 2'd1 ? 1'd1;
early_reset_static_seq[done] = ud.out;
adder0.left = fsm.out;
adder0.right = 2'd1;
fsm.in = fsm.out == 2'd0 & go ? adder0.out;
adder.left = fsm.out;
adder.right = 2'd1;
fsm.in = fsm.out == 2'd0 & go ? adder.out;
fsm.write_en = fsm.out == 2'd0 & go ? 1'd1;
fsm.in = fsm.out != 2'd1 & fsm.out != 2'd0 ? adder0.out;
fsm.in = fsm.out != 2'd1 & fsm.out != 2'd0 ? adder.out;
fsm.write_en = fsm.out != 2'd1 & fsm.out != 2'd0 ? 1'd1;
fsm.in = fsm.out == 2'd1 & 1'b1 & fsm0.out == 3'd4 ? 2'd0;
fsm.write_en = fsm.out == 2'd1 & 1'b1 & fsm0.out == 3'd4 ? 1'd1;
Expand All @@ -34,9 +34,9 @@ static<6> component do_add(left: 32, right: 32, @go go: 1, @clk clk: 1, @reset r
add.left = r.out;
r.in = add.out;
early_reset_a[done] = ud0.out;
adder.left = fsm0.out;
adder.right = 3'd1;
fsm0.in = fsm0.out != 3'd4 ? adder.out;
adder0.left = fsm0.out;
adder0.right = 3'd1;
fsm0.in = fsm0.out != 3'd4 ? adder0.out;
fsm0.write_en = fsm0.out != 3'd4 ? 1'd1;
fsm0.in = fsm0.out == 3'd4 ? 3'd0;
fsm0.write_en = fsm0.out == 3'd4 ? 1'd1;
Expand All @@ -46,11 +46,11 @@ static<6> component do_add(left: 32, right: 32, @go go: 1, @clk clk: 1, @reset r
add.left = go & fsm.out == 2'd0 ? left;
r.in = go & fsm.out == 2'd0 ? add.out;
early_reset_a[go] = fsm.out == 2'd1 ? 1'd1;
adder0.left = fsm.out;
adder0.right = 2'd1;
fsm.in = fsm.out == 2'd0 & go ? adder0.out;
adder.left = fsm.out;
adder.right = 2'd1;
fsm.in = fsm.out == 2'd0 & go ? adder.out;
fsm.write_en = fsm.out == 2'd0 & go ? 1'd1;
fsm.in = fsm.out != 2'd1 & fsm.out != 2'd0 ? adder0.out;
fsm.in = fsm.out != 2'd1 & fsm.out != 2'd0 ? adder.out;
fsm.write_en = fsm.out != 2'd1 & fsm.out != 2'd0 ? 1'd1;
fsm.in = fsm.out == 2'd1 & 1'b1 & fsm0.out == 3'd4 ? 2'd0;
fsm.write_en = fsm.out == 2'd1 & 1'b1 & fsm0.out == 3'd4 ? 1'd1;
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8 changes: 4 additions & 4 deletions tests/passes/compile-static-interface/compile-static-interface.expect
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Original file line number Diff line number Diff line change
Expand Up @@ -23,8 +23,8 @@ static<2> component do_add(left: 32, right: 32, @go go: 1, @clk clk: 1, @reset r
adder.right = 2'd1;
fsm.in = fsm.out == 2'd0 & go ? adder.out;
fsm.write_en = fsm.out == 2'd0 & go ? 1'd1;
fsm.in = fsm.out != 2'd1 & fsm.out != 2'd0 ? adder.out;
fsm.write_en = fsm.out != 2'd1 & fsm.out != 2'd0 ? 1'd1;
fsm.in = fsm.out != 2'd0 & fsm.out != 2'd1 ? adder.out;
fsm.write_en = fsm.out != 2'd0 & fsm.out != 2'd1 ? 1'd1;
fsm.in = fsm.out == 2'd1 ? 2'd0;
fsm.write_en = fsm.out == 2'd1 ? 1'd1;
}
Expand All @@ -40,8 +40,8 @@ static<2> component do_add(left: 32, right: 32, @go go: 1, @clk clk: 1, @reset r
adder.right = 2'd1;
fsm.in = fsm.out == 2'd0 & go ? adder.out;
fsm.write_en = fsm.out == 2'd0 & go ? 1'd1;
fsm.in = fsm.out != 2'd1 & fsm.out != 2'd0 ? adder.out;
fsm.write_en = fsm.out != 2'd1 & fsm.out != 2'd0 ? 1'd1;
fsm.in = fsm.out != 2'd0 & fsm.out != 2'd1 ? adder.out;
fsm.write_en = fsm.out != 2'd0 & fsm.out != 2'd1 ? 1'd1;
fsm.in = fsm.out == 2'd1 ? 2'd0;
fsm.write_en = fsm.out == 2'd1 ? 1'd1;
}
Expand Down
26 changes: 13 additions & 13 deletions tests/passes/compile-static-interface/interface-one-hot.expect
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Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,8 @@ static<6> component do_add<"promoted"=1>(left: 32, right: 32, @go go: 1, @clk cl
r = std_reg(32);
@generated fsm = std_reg(2);
@generated fsm0 = std_reg(3);
@generated adder = std_add(3);
@generated adder0 = std_add(2);
@generated adder = std_add(2);
@generated adder0 = std_add(3);
@generated ud = undef(1);
@generated ud0 = undef(1);
@generated sig_reg = std_reg(1);
Expand All @@ -20,11 +20,11 @@ static<6> component do_add<"promoted"=1>(left: 32, right: 32, @go go: 1, @clk cl
r.in = go & fsm.out == 2'd0 ? add.out;
early_reset_a[go] = fsm.out == 2'd1 ? 1'd1;
early_reset_static_seq[done] = ud.out;
adder0.left = fsm.out;
adder0.right = 2'd1;
fsm.in = fsm.out == 2'd0 & go ? adder0.out;
adder.left = fsm.out;
adder.right = 2'd1;
fsm.in = fsm.out == 2'd0 & go ? adder.out;
fsm.write_en = fsm.out == 2'd0 & go ? 1'd1;
fsm.in = fsm.out != 2'd1 & fsm.out != 2'd0 ? adder0.out;
fsm.in = fsm.out != 2'd1 & fsm.out != 2'd0 ? adder.out;
fsm.write_en = fsm.out != 2'd1 & fsm.out != 2'd0 ? 1'd1;
fsm.in = fsm.out == 2'd1 & 1'b1 & fsm0.out == 3'd4 ? 2'd0;
fsm.write_en = fsm.out == 2'd1 & 1'b1 & fsm0.out == 3'd4 ? 1'd1;
Expand All @@ -35,9 +35,9 @@ static<6> component do_add<"promoted"=1>(left: 32, right: 32, @go go: 1, @clk cl
add.left = r.out;
r.in = add.out;
early_reset_a[done] = ud0.out;
adder.left = fsm0.out;
adder.right = 3'd1;
fsm0.in = fsm0.out != 3'd4 ? adder.out;
adder0.left = fsm0.out;
adder0.right = 3'd1;
fsm0.in = fsm0.out != 3'd4 ? adder0.out;
fsm0.write_en = fsm0.out != 3'd4 ? 1'd1;
fsm0.in = fsm0.out == 3'd4 ? 3'd0;
fsm0.write_en = fsm0.out == 3'd4 ? 1'd1;
Expand All @@ -47,11 +47,11 @@ static<6> component do_add<"promoted"=1>(left: 32, right: 32, @go go: 1, @clk cl
add.left = go & fsm.out == 2'd0 ? left;
r.in = go & fsm.out == 2'd0 ? add.out;
early_reset_a[go] = fsm.out == 2'd1 ? 1'd1;
adder0.left = fsm.out;
adder0.right = 2'd1;
fsm.in = fsm.out == 2'd0 & go ? adder0.out;
adder.left = fsm.out;
adder.right = 2'd1;
fsm.in = fsm.out == 2'd0 & go ? adder.out;
fsm.write_en = fsm.out == 2'd0 & go ? 1'd1;
fsm.in = fsm.out != 2'd1 & fsm.out != 2'd0 ? adder0.out;
fsm.in = fsm.out != 2'd1 & fsm.out != 2'd0 ? adder.out;
fsm.write_en = fsm.out != 2'd1 & fsm.out != 2'd0 ? 1'd1;
fsm.in = fsm.out == 2'd1 & 1'b1 & fsm0.out == 3'd4 ? 2'd0;
fsm.write_en = fsm.out == 2'd1 & 1'b1 & fsm0.out == 3'd4 ? 1'd1;
Expand Down
26 changes: 13 additions & 13 deletions tests/passes/compile-static/interface-and-cs.expect
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Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,8 @@ static<6> component do_add(left: 32, right: 32, @go go: 1, @clk clk: 1, @reset r
r = std_reg(32);
@generated fsm = std_reg(2);
@generated fsm0 = std_reg(3);
@generated adder = std_add(3);
@generated adder0 = std_add(2);
@generated adder = std_add(2);
@generated adder0 = std_add(3);
@generated ud = undef(1);
@generated ud0 = undef(1);
}
Expand All @@ -19,11 +19,11 @@ static<6> component do_add(left: 32, right: 32, @go go: 1, @clk clk: 1, @reset r
r.in = go & fsm.out == 2'd0 ? add.out;
early_reset_a[go] = fsm.out == 2'd1 ? 1'd1;
early_reset_static_seq[done] = ud.out;
adder0.left = fsm.out;
adder0.right = 2'd1;
fsm.in = fsm.out == 2'd0 & go ? adder0.out;
adder.left = fsm.out;
adder.right = 2'd1;
fsm.in = fsm.out == 2'd0 & go ? adder.out;
fsm.write_en = fsm.out == 2'd0 & go ? 1'd1;
fsm.in = fsm.out != 2'd1 & fsm.out != 2'd0 ? adder0.out;
fsm.in = fsm.out != 2'd1 & fsm.out != 2'd0 ? adder.out;
fsm.write_en = fsm.out != 2'd1 & fsm.out != 2'd0 ? 1'd1;
fsm.in = fsm.out == 2'd1 & 1'b1 & fsm0.out == 3'd4 ? 2'd0;
fsm.write_en = fsm.out == 2'd1 & 1'b1 & fsm0.out == 3'd4 ? 1'd1;
Expand All @@ -34,9 +34,9 @@ static<6> component do_add(left: 32, right: 32, @go go: 1, @clk clk: 1, @reset r
add.left = r.out;
r.in = add.out;
early_reset_a[done] = ud0.out;
adder.left = fsm0.out;
adder.right = 3'd1;
fsm0.in = fsm0.out != 3'd4 ? adder.out;
adder0.left = fsm0.out;
adder0.right = 3'd1;
fsm0.in = fsm0.out != 3'd4 ? adder0.out;
fsm0.write_en = fsm0.out != 3'd4 ? 1'd1;
fsm0.in = fsm0.out == 3'd4 ? 3'd0;
fsm0.write_en = fsm0.out == 3'd4 ? 1'd1;
Expand All @@ -46,11 +46,11 @@ static<6> component do_add(left: 32, right: 32, @go go: 1, @clk clk: 1, @reset r
add.left = go & fsm.out == 2'd0 ? left;
r.in = go & fsm.out == 2'd0 ? add.out;
early_reset_a[go] = fsm.out == 2'd1 ? 1'd1;
adder0.left = fsm.out;
adder0.right = 2'd1;
fsm.in = fsm.out == 2'd0 & go ? adder0.out;
adder.left = fsm.out;
adder.right = 2'd1;
fsm.in = fsm.out == 2'd0 & go ? adder.out;
fsm.write_en = fsm.out == 2'd0 & go ? 1'd1;
fsm.in = fsm.out != 2'd1 & fsm.out != 2'd0 ? adder0.out;
fsm.in = fsm.out != 2'd1 & fsm.out != 2'd0 ? adder.out;
fsm.write_en = fsm.out != 2'd1 & fsm.out != 2'd0 ? 1'd1;
fsm.in = fsm.out == 2'd1 & 1'b1 & fsm0.out == 3'd4 ? 2'd0;
fsm.write_en = fsm.out == 2'd1 & 1'b1 & fsm0.out == 3'd4 ? 1'd1;
Expand Down
26 changes: 13 additions & 13 deletions tests/passes/compile-static/separate-fsms.expect
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Original file line number Diff line number Diff line change
Expand Up @@ -9,9 +9,9 @@ component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
d = std_reg(2);
@generated fsm = std_reg(2);
@generated fsm0 = std_reg(3);
@generated adder = std_add(3);
@generated adder = std_add(2);
@generated adder0 = std_add(3);
@generated adder1 = std_add(2);
@generated adder1 = std_add(3);
@generated ud = undef(1);
@generated ud0 = undef(1);
@generated ud1 = undef(1);
Expand All @@ -26,22 +26,22 @@ component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
early_reset_A[go] = fsm.out == 2'd0 ? 1'd1;
early_reset_D[go] = fsm.out == 2'd1 ? 1'd1;
early_reset_run_A_and_D[done] = ud.out;
adder1.left = fsm.out;
adder1.right = 2'd1;
fsm.in = fsm.out == 2'd0 & 1'b1 & fsm0.out == 3'd3 ? adder1.out;
fsm.write_en = fsm.out == 2'd0 & 1'b1 & fsm0.out == 3'd3 ? 1'd1;
fsm.in = !(fsm.out == 2'd0 | fsm.out == 2'd1) ? adder1.out;
adder.left = fsm.out;
adder.right = 2'd1;
fsm.in = !(fsm.out == 2'd0 | fsm.out == 2'd1) ? adder.out;
fsm.write_en = !(fsm.out == 2'd0 | fsm.out == 2'd1) ? 1'd1;
fsm.in = fsm.out == 2'd1 & 1'b1 & fsm0.out == 3'd1 ? 2'd0;
fsm.write_en = fsm.out == 2'd1 & 1'b1 & fsm0.out == 3'd1 ? 1'd1;
fsm.in = fsm.out == 2'd0 & 1'b1 & fsm0.out == 3'd3 ? adder.out;
fsm.write_en = fsm.out == 2'd0 & 1'b1 & fsm0.out == 3'd3 ? 1'd1;
}
group early_reset_A {
a.in = 2'd0;
a.write_en = 1'd1;
early_reset_A[done] = ud0.out;
adder.left = fsm0.out;
adder.right = 3'd1;
fsm0.in = fsm0.out != 3'd3 ? adder.out;
adder0.left = fsm0.out;
adder0.right = 3'd1;
fsm0.in = fsm0.out != 3'd3 ? adder0.out;
fsm0.write_en = fsm0.out != 3'd3 ? 1'd1;
fsm0.in = fsm0.out == 3'd3 ? 3'd0;
fsm0.write_en = fsm0.out == 3'd3 ? 1'd1;
Expand All @@ -50,9 +50,9 @@ component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
d.in = 2'd0;
d.write_en = 1'd1;
early_reset_D[done] = ud1.out;
adder0.left = fsm0.out;
adder0.right = 3'd1;
fsm0.in = fsm0.out != 3'd1 ? adder0.out;
adder1.left = fsm0.out;
adder1.right = 3'd1;
fsm0.in = fsm0.out != 3'd1 ? adder1.out;
fsm0.write_en = fsm0.out != 3'd1 ? 1'd1;
fsm0.in = fsm0.out == 3'd1 ? 3'd0;
fsm0.write_en = fsm0.out == 3'd1 ? 1'd1;
Expand Down

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