Sort ports when compiling refs (fix #2016) (#2018)

calyxir · Apr 25, 2024 · c286cb7 · c286cb7
1 parent 56b99c5
commit c286cb7
Showing 1 changed file with 6 additions and 3 deletions.
diff --git a/calyx-opt/src/passes/compile_invoke.rs b/calyx-opt/src/passes/compile_invoke.rs
@@ -75,9 +75,12 @@ impl RefPortMap {
     /// Get all of the newly added ports associated with a component that had
     /// ref cells
     fn get_ports(&self, comp_name: &ir::Id) -> Option<Vec<RRC<ir::Port>>> {
-        self.0
-            .get(comp_name)
-            .map(|map| map.values().cloned().collect())
+        self.0.get(comp_name).map(|map| {
+            map.values()
+                .cloned()
+                .sorted_by(|a, b| a.borrow().name.cmp(&b.borrow().name))
+                .collect()
+        })
     }
 }