Change generated kernel.xml axi manager port width to 512 (#1074)

* Changed axi manager port width to 512 * Added comments regarding kernel width Co-authored-by: Nathaniel Navarro <[email protected]>
calyxir · Jul 7, 2022 · cbbb2c5 · cbbb2c5
1 parent 4c2d932
commit cbbb2c5
Showing 1 changed file with 4 additions and 1 deletion.
diff --git a/src/backend/xilinx/xml.rs b/src/backend/xilinx/xml.rs
@@ -150,7 +150,10 @@ impl Backend for XilinxXmlBackend {
                 name: axi_name,
                 mode: "master",
                 range: "0xFFFFFFFFFFFFFFFF",
-                data_width: 64,
+                // Width should match the bus data width of memory modules
+                // described in hardware, for example see
+                // https://github.com/cucapra/calyx/blob/c2b12a0fe6b1ee3aaaae0c66e7c4619ee6c82614/src/backend/xilinx/toplevel.rs#L58
+                data_width: 512,
                 port_type: "addressable",
                 base: "0x0",
             });