Memories sent fix (#1075)

* Change memories_sent to use bit and operator

Memories_sent is now asserted when all of the x_send_done signals are
asserted. Before, each bit corresponded to a different memory being
done.

This avoids having computations finish when any one of the memories
is done.

* Removes old comments

* Removed uneeded if-else and assert memory count

We assume that at least 1 memory is present, assertion is
made at top of toplevel function

* Fixed formatting

Co-authored-by: Nathaniel Navarro <[email protected]>

src/backend/xilinx/toplevel.rs

@@ -95,6 +95,7 @@ fn top_level(
     data_width: u64,
     memories: &[String],
 ) -> v::Module {
+    assert!(!memories.is_empty()); // At least 1 memory should exist within the toplevel
     let mut module = v::Module::new("Toplevel");
 
     // add system signals
@@ -253,7 +254,7 @@ fn top_level(
 
 fn host_transfer_fsm(module: &mut v::Module, memories: &[String]) {
     module.add_decl(v::Decl::new_wire("memories_copied", 1));
-    module.add_decl(v::Decl::new_reg("memories_sent", memories.len() as u64));
+    module.add_decl(v::Decl::new_reg("memories_sent", 1));
     module.add_stmt(v::Parallel::Assign(
         "memories_copied".into(),
         if memories.is_empty() {
@@ -285,20 +286,18 @@ fn host_transfer_fsm(module: &mut v::Module, memories: &[String]) {
 
     let mut parallel = v::ParallelProcess::new_always();
     parallel.set_event(v::Sequential::new_posedge("ap_clk"));
+
     let mut ifelse = v::SequentialIfElse::new(fsm.state_is("send"));
-    if memories.len() == 1 {
-        ifelse.add_seq(v::Sequential::new_nonblk_assign(
-            "memories_sent",
-            format!("{}_send_done", memories[0]),
-        ));
-    } else {
-        for (idx, mem) in memories.iter().enumerate() {
-            ifelse.add_seq(v::Sequential::new_nonblk_assign(
-                v::Expr::new_index_bit("memories_sent", idx as i32),
-                format!("{}_send_done", mem),
-            ));
-        }
-    }
+    ifelse.add_seq(v::Sequential::new_nonblk_assign(
+        "memories_sent",
+        memories[1..].iter().fold(
+            format!("{}_send_done", memories[0]).into(),
+            |acc, elem| {
+                v::Expr::new_bit_and(acc, format!("{}_send_done", elem))
+            },
+        ),
+    ));
+
     ifelse.set_else(v::Sequential::new_nonblk_assign("memories_sent", 0));
     parallel.add_seq(ifelse);
     module.add_stmt(parallel);