adapt tests to use baa

interp/Cargo.toml

@@ -46,7 +46,7 @@ calyx-frontend = { path = "../calyx-frontend" }
 btor2i = { path = "../tools/btor2/btor2i" }
 
 ciborium = "0.2.2"
-baa = { version = "0.4.1", features = ["bigint", "serde1", "fraction1"] }
+baa = { version = "0.5.1", features = ["bigint", "serde1", "fraction1"] }
 
 [dev-dependencies]
 proptest = "1.0.0"

interp/proptest-regressions/tests/values.txt

@@ -0,0 +1,7 @@
+# Seeds for failure cases proptest has generated in the past. It is
+# automatically read and these particular cases re-run before any
+# novel cases are generated.
+#
+# It is recommended to check this file in to source control so that
+# everyone who runs the test benefits from these saved cases.
+cc 8bfbc0242b84cd41283ecc9c000e88751215cf3bbef619b67f08dcb64f8ab602 # shrinks to input = 0

interp/src/flatten/flat_ir/base.rs

@@ -592,10 +592,10 @@ impl PortValue {
                 PrintCode::Unsigned => format!("{}", v.to_big_uint()),
                 PrintCode::Signed => format!("{}", v.to_big_int()),
                 PrintCode::UFixed(num) => {
-                    format!("{}", v.to_unsigned_fixed_point(num))
+                    format!("{}", v.to_unsigned_fixed_point(num).unwrap())
                 }
                 PrintCode::SFixed(num) => {
-                    format!("{}", v.to_signed_fixed_point(num))
+                    format!("{}", v.to_signed_fixed_point(num).unwrap())
                 }
                 PrintCode::Binary => format!("{}", v.to_bit_str()),
             }

interp/src/flatten/primitives/builder.rs

@@ -52,8 +52,8 @@ pub fn build_primitive(
             SingleWidthType::Neq => Box::new(StdNeq::new(base_port)),
             SingleWidthType::Ge => Box::new(StdGe::new(base_port)),
             SingleWidthType::Le => Box::new(StdLe::new(base_port)),
-            SingleWidthType::Lsh => Box::new(StdLsh::new(base_port, *width)),
-            SingleWidthType::Rsh => Box::new(StdRsh::new(base_port, *width)),
+            SingleWidthType::Lsh => Box::new(StdLsh::new(base_port)),
+            SingleWidthType::Rsh => Box::new(StdRsh::new(base_port)),
             SingleWidthType::Mux => Box::new(StdMux::new(base_port)),
             SingleWidthType::Wire => Box::new(StdWire::new(base_port)),
             SingleWidthType::SignedAdd => Box::new(StdAdd::new(base_port)),
@@ -83,7 +83,7 @@ pub fn build_primitive(
                 Box::new(Sqrt::<false>::new(base_port, *width, None))
             }
             SingleWidthType::UnsynMult => {
-                Box::new(StdUnsynMult::new(base_port, *width))
+                Box::new(StdUnsynMult::new(base_port))
             }
             SingleWidthType::UnsynDiv => {
                 Box::new(StdUnsynDiv::new(base_port, *width))
@@ -92,7 +92,7 @@ pub fn build_primitive(
                 Box::new(StdUnsynMod::new(base_port, *width))
             }
             SingleWidthType::UnsynSMult => {
-                Box::new(StdUnsynSmult::new(base_port, *width))
+                Box::new(StdUnsynSmult::new(base_port))
             }
             SingleWidthType::UnsynSDiv => {
                 Box::new(StdUnsynSdiv::new(base_port, *width))
@@ -142,18 +142,15 @@ pub fn build_primitive(
             DoubleWidthType::Pad => Box::new(StdPad::new(base_port, *width2)),
         },
         CellPrototype::TripleWidth {
-            op,
-            width1,
-            width2,
-            width3,
+            op, width1, width2, ..
         } => match op {
             TripleWidthType::Cat => {
                 // Turns out under the assumption that the primitive is well formed,
                 // none of these parameter values are actually needed
                 Box::new(StdCat::new(base_port))
             }
             TripleWidthType::BitSlice => {
-                Box::new(StdBitSlice::new(base_port, *width1, *width2, *width3))
+                Box::new(StdBitSlice::new(base_port, *width1, *width2))
             }
         },
 

interp/src/flatten/primitives/combinational.rs

@@ -111,12 +111,12 @@ comb_primitive!(StdFpSub(left [0], right [1]) -> (out [2]) {
 });
 
 // ===================== Shift Operations ======================
-comb_primitive!(StdLsh[WIDTH](left [0], right [1]) -> (out [2]) {
+comb_primitive!(StdLsh(left [0], right [1]) -> (out [2]) {
     all_defined!(left, right);
     Ok(Some(left.shift_left(right)))
 });
 
-comb_primitive!(StdRsh[WIDTH](left [0], right [1]) -> (out [2]) {
+comb_primitive!(StdRsh(left [0], right [1]) -> (out [2]) {
     all_defined!(left, right);
     Ok(Some(left.shift_right(right)))
 });
@@ -230,14 +230,14 @@ comb_primitive!(StdCat(left [0], right [1]) -> (out [2]) {
     Ok(Some(left.concat(right).into()))
 });
 
-comb_primitive!(StdBitSlice[START_IDX, END_IDX, OUT_WIDTH](input [0]) -> (out [1]) {
+comb_primitive!(StdBitSlice[START_IDX, END_IDX](input [0]) -> (out [1]) {
     all_defined!(input);
     let (msb, lsb) = (END_IDX, START_IDX);
     Ok(Some(input.slice(msb, lsb)))
 });
 
 // ===================== Unsynthesizeable Operations ======================
-comb_primitive!(StdUnsynMult[WIDTH](left [0], right [1]) -> (out [2]) {
+comb_primitive!(StdUnsynMult(left [0], right [1]) -> (out [2]) {
     all_defined!(left, right);
     Ok(Some(left.mul(right)))
 });
@@ -248,7 +248,7 @@ comb_primitive!(StdUnsynDiv[WIDTH](left [0], right [1]) -> (out [2]) {
     Ok(Some(BitVecValue::from_big_uint(&res, WIDTH)))
 });
 
-comb_primitive!(StdUnsynSmult[WIDTH](left [0], right [1]) -> (out [2]) {
+comb_primitive!(StdUnsynSmult(left [0], right [1]) -> (out [2]) {
     all_defined!(left, right);
     // FIXME: is there a difference for signed?
     Ok(Some(left.mul(right)))

interp/src/macros.rs

@@ -39,15 +39,15 @@ macro_rules! lit_or_id {
 /// ```
 macro_rules! port_bindings {
     ( $binds: ident; $( $port: ident -> ($val: tt, $width: tt) ),+ ) => {
-        $( let $port = $crate::values::BitVecValue::from($crate::lit_or_id!($val), $crate::lit_or_id!($width)); )+
+        $( let $port = baa::BitVecValue::from_u64($crate::lit_or_id!($val), $crate::lit_or_id!($width)); )+
         let $binds = vec![ $( (calyx_ir::Id::from($crate::in_fix!($port)), &$port) ),+ ];
     }
 }
 
 /// Helper macro to generate validation checks for the input passed to primitives
 /// ```
 ///  # use interp::validate;
-///  # use interp::values::BitVecValue;
+///  # use baa::BitVecValue;
 ///  # let input = [("left", [4,4,4,4])];
 ///  # let inputs = &input;
 ///  # let width = 4;
@@ -73,7 +73,7 @@ macro_rules! validate {
 /// primitives, does not error on unknown ports
 /// ```
 ///  # use interp::validate_friendly;
-///  # use interp::values::BitVecValue;
+///  # use baa::BitVecValue;
 ///  # let input = [("left", [4,4,4,4])];
 ///  # let inputs = &input;
 ///  # let width = 4;

interp/src/serialization/formatting.rs

@@ -132,8 +132,12 @@ impl Entry {
         match code {
             PrintCode::Unsigned => val.to_u64().unwrap().into(),
             PrintCode::Signed => val.to_i64().unwrap().into(),
-            PrintCode::UFixed(f) => val.to_unsigned_fixed_point(*f).into(),
-            PrintCode::SFixed(f) => val.to_signed_fixed_point(*f).into(),
+            PrintCode::UFixed(f) => {
+                val.to_unsigned_fixed_point(*f).unwrap().into()
+            }
+            PrintCode::SFixed(f) => {
+                val.to_signed_fixed_point(*f).unwrap().into()
+            }
             PrintCode::Binary => Entry::Value(val.clone()),
         }
     }