Revert more fud2 stuff

fud2/src/lib.rs

@@ -83,21 +83,6 @@ fn setup_mrxl(
     (mrxl, mrxl_setup)
 }
 
-fn setup_tb(bld: &mut DriverBuilder, verilog: StateRef) {
-    let tb = bld.state("tb", &[]);
-    let tb_setup = bld.setup("Testbench executable", |e| {
-        e.var("calyx-tb-exe", "tb")?;
-        e.config_var("calyx-tb-test", "tb.test")?; // todo multi input op
-        e.config_var("calyx-tb-config-file", "tb.config-file")?;
-        e.rule(
-            "calyx-to-tb",
-            "$calyx-tb-exe $in --test $calyx-tb-test --using cocotb --config $calyx-tb-config-file",
-        )?;
-        Ok(())
-    });
-    bld.rule(&[tb_setup], verilog, tb, "test");
-}
-
 pub fn build_driver(bld: &mut DriverBuilder) {
     // The verilog state
     let verilog = bld.state("verilog", &["sv", "v"]);
@@ -108,8 +93,6 @@ pub fn build_driver(bld: &mut DriverBuilder) {
     // MrXL.
     setup_mrxl(bld, calyx);
 
-    setup_tb(bld, verilog);
-
     // Shared machinery for RTL simulators.
     let dat = bld.state("dat", &["json"]);
     let vcd = bld.state("vcd", &["vcd"]);

fud2/tests/snapshots/tests__test@plan_verilog-to-tb.snap.new

@@ -0,0 +1,13 @@
+---
+source: fud2/tests/tests.rs
+assertion_line: 66
+description: "emit plan: verilog-to-tb"
+---
+build-tool = fud2
+rule get-rsrc
+  command = $build-tool get-rsrc $out
+
+
+build /output.ext: verilog-to-tb /input.ext
+
+default /output.ext