Fix incorrect documentation command. Fixes #1593

docs/fud/examples.md

@@ -12,7 +12,7 @@ to compile Calyx programs to Verilog.
 # to Verilog. We must explicitly specify the input
 # file type because it can not be guessed from
 # the file extension.
-fud exec examples/futil/simple.expect --from futil --to verilog
+fud exec examples/futil/simple.futil --from calyx --to verilog
 ```
 
 Fud can explain its execution plan when running a complex sequence of

docs/fud/multiple-paths.md

@@ -8,8 +8,8 @@ paths can be used to generate VCD files from Dahlia programs:
 ```
 % fud e --from dahlia --to vcd
 [fud] ERROR: Multiple stage pipelines can transform dahlia to vcd:
-dahlia → futil → verilog → vcd
-dahlia → futil → icarus-verilog → vcd
+dahlia → calyx → verilog → vcd
+dahlia → calyx → icarus-verilog → vcd
 Use the --through flag to select an intermediate stage
 ```