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Added --disable-init flag to fud xclbin stage #1085

Merged
merged 3 commits into from
Jul 7, 2022
Merged

Added --disable-init flag to fud xclbin stage #1085

merged 3 commits into from
Jul 7, 2022

Commits on Jul 7, 2022

  1. Added --disable-init flag to fud xclbin stage 

    This disables all automatic initialization when generating verilog, but
only for Xilinx execution. At some point thid may be revisited to a
broader "is initilization correct."

Previously, behavior was wonky because we were treating certain signals
as both registers (in initilization) and wires (later on).
    @nathanielnrn
    nathanielnrn committed Jul 7, 2022
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  2. Change generated kernel.xml axi manager port width to 512 (#1074) 

    * Changed axi manager port width to 512

* Added comments regarding kernel width

Co-authored-by: Nathaniel Navarro <[email protected]>
    @nathanielnrn
    nathanielnrn and nathanielnrn committed Jul 7, 2022
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  3. Merge branch 'master' into wire-init-fix

    @nathanielnrn
    nathanielnrn committed Jul 7, 2022
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