Supporting external writes to registers

Cargo.toml

@@ -48,6 +48,7 @@ calyx-ir = { path = "calyx-ir", version = "0.6.1" }
 calyx-frontend = { path = "calyx-frontend", version = "0.6.1" }
 calyx-opt = { path = "calyx-opt", version = "0.6.1" }
 calyx-backend = { path = "calyx-backend", version = "0.6.1" }
+calyx-stdlib = { path = "calyx-stdlib", version = "0.6.1" }
 
 [workspace.dependencies.petgraph]
 version = "0.6"

calyx-backend/Cargo.toml

@@ -26,6 +26,7 @@ smallvec.workspace = true
 calyx-utils.workspace = true
 calyx-frontend.workspace = true
 calyx-ir.workspace = true
+calyx-stdlib.workspace = true
 
 csv = { version = "1.1", optional = true }
 vast = "0.3.1"

calyx-backend/src/verilog.rs

@@ -5,6 +5,7 @@
 
 use crate::traits::Backend;
 use calyx_ir::{self as ir, Control, FlatGuard, Group, Guard, GuardRef, RRC};
+use calyx_stdlib as primitives;
 use calyx_utils::{CalyxResult, Error, OutputFile};
 use ir::Nothing;
 use itertools::Itertools;
@@ -18,21 +19,6 @@ use vast::v17::ast as v;
 #[derive(Default)]
 pub struct VerilogBackend;
 
-// input string should be the cell type name of a memory cell. In other words one
-// of "seq/std_mem_d_1/2/3/4". Becase we define seq_mem_d2/3/4 in terms of seq_mem_d1
-// we need another layer of memory access to get the actual memory array in verilog
-// for these mem types.
-// In other words, for memories not defined in terms of another memory, we can just use
-// "mem" to access them. But for memories defined in terms of another memory,
-// which are seq_mem_d2/3/4, we need "mem.mem" to access them.
-fn get_mem_str(mem_type: &str) -> &str {
-    if mem_type.contains("d1") || mem_type.contains("std_mem") {
-        "mem"
-    } else {
-        "mem.mem"
-    }
-}
-
 /// Checks to make sure that there are no holes being
 /// used in a guard.
 fn validate_guard(guard: &ir::Guard<Nothing>) -> bool {
@@ -778,22 +764,29 @@ fn memory_read_write(comp: &ir::Component) -> Vec<v::Stmt> {
         .cells
         .iter()
         .filter_map(|cell| {
-            let is_external = cell.borrow().get_attribute(ir::BoolAttr::External).is_some();
-            if is_external
-                && cell
-                    .borrow()
-                    .type_name()
-                    // HACK: Check if the name of the primitive contains the string "mem"
-                    .map(|proto| proto.id.as_str().contains("mem"))
-                    .unwrap_or_default()
-            {
-                Some((
-                    cell.borrow().name().id,
-                    cell.borrow().type_name().unwrap_or_else(|| unreachable!("tried to add a memory cell but there was no type name")),
-                ))
-            } else {
-                None
+            let cell = cell.borrow();
+            if !cell.has_attribute(ir::BoolAttr::External) {
+                return None;
+            }
+            let loadable = cell
+                .type_name()
+                .map(|n| primitives::is_loadable(n.id.as_str()))
+                .unwrap_or_default();
+            if !loadable {
+                log::warn!(
+                    "Cell {} is marked as external but is not loadable",
+                    cell.name().id
+                );
+                return None;
             }
+            Some((
+                cell.name().id,
+                cell.type_name().unwrap_or_else(|| {
+                    unreachable!(
+                        "tried to add a memory cell but there was no type name"
+                    )
+                }),
+            ))
         })
         .collect_vec();
 
@@ -827,7 +820,7 @@ fn memory_read_write(comp: &ir::Component) -> Vec<v::Stmt> {
         )));
 
     memories.iter().for_each(|(name, mem_type)| {
-        let mem_access_str = get_mem_str(mem_type.id.as_str());
+        let mem_access_str = primitives::load_path(mem_type.id.as_str());
         initial_block.add_seq(v::Sequential::new_seqexpr(v::Expr::new_call(
             "$readmemh",
             vec![
@@ -844,7 +837,7 @@ fn memory_read_write(comp: &ir::Component) -> Vec<v::Stmt> {
 
     let mut final_block = v::ParallelProcess::new_final();
     memories.iter().for_each(|(name, mem_type)| {
-        let mem_access_str = get_mem_str(mem_type.id.as_str());
+        let mem_access_str = primitives::load_path(mem_type.id.as_str());
 
         final_block.add_seq(v::Sequential::new_seqexpr(v::Expr::new_call(
             "$writememh",

calyx-ir/src/structure.rs

@@ -422,6 +422,11 @@ impl Cell {
         self.attributes.get(attr.into())
     }
 
+    /// Return true if this cell has the given attribute.
+    pub fn has_attribute<A: Into<Attribute>>(&self, attr: A) -> bool {
+        self.attributes.has(attr.into())
+    }
+
     /// Add a new attribute to the group.
     pub fn add_attribute<A: Into<Attribute>>(&mut self, attr: A, value: u64) {
         self.attributes.insert(attr.into(), value);

calyx-stdlib/src/lib.rs

@@ -1,3 +1,8 @@
+mod memories;
 mod primitives;
 
+pub use memories::{
+    is_loadable, load_path, SEQ_MEM_D1, SEQ_MEM_D2, SEQ_MEM_D3, SEQ_MEM_D4,
+    STD_MEM_D1, STD_MEM_D2, STD_MEM_D3, STD_MEM_D4, STD_REG,
+};
 pub use primitives::{COMPILE_LIB, KNOWN_LIBS};

calyx-stdlib/src/memories.rs

@@ -0,0 +1,44 @@
+//! Verilog-level names for the primitives
+
+/// Register
+pub const STD_REG: &str = "std_reg";
+
+// Memories
+pub const STD_MEM_D1: &str = "std_mem_d1";
+pub const STD_MEM_D2: &str = "std_mem_d2";
+pub const STD_MEM_D3: &str = "std_mem_d3";
+pub const STD_MEM_D4: &str = "std_mem_d4";
+
+// Sequential Memories
+pub const SEQ_MEM_D1: &str = "seq_mem_d1";
+pub const SEQ_MEM_D2: &str = "seq_mem_d2";
+pub const SEQ_MEM_D3: &str = "seq_mem_d3";
+pub const SEQ_MEM_D4: &str = "seq_mem_d4";
+
+/// The primitive supports loading input value from a file using `readmemh` and
+/// `writememh` calls in Verilog.
+pub fn is_loadable(type_name: &str) -> bool {
+    matches!(
+        type_name,
+        STD_REG
+            | STD_MEM_D1
+            | STD_MEM_D2
+            | STD_MEM_D3
+            | STD_MEM_D4
+            | SEQ_MEM_D1
+            | SEQ_MEM_D2
+            | SEQ_MEM_D3
+            | SEQ_MEM_D4
+    )
+}
+
+/// Verilog module path to load values into.
+pub fn load_path(type_name: &str) -> &str {
+    match type_name {
+        STD_REG => "mem",
+        STD_MEM_D1 | STD_MEM_D2 | STD_MEM_D3 | STD_MEM_D4 => "mem",
+        SEQ_MEM_D1 => "mem",
+        SEQ_MEM_D2 | SEQ_MEM_D3 | SEQ_MEM_D4 => "mem.mem",
+        _ => unreachable!("Unknown loadable primitive: {type_name}"),
+    }
+}

primitives/compile.futil

@@ -31,12 +31,14 @@ primitive std_reg<"state_share"=1>[WIDTH](
 )
 // ANCHOR_END: std_reg_def
 {
+  logic [WIDTH-1:0] mem;
+  assign out = mem;
   always_ff @(posedge clk) begin
     if (reset) begin
-       out <= 0;
+       mem <= 0;
        done <= 0;
     end else if (write_en) begin
-      out <= in;
+      mem <= in;
       done <= 1'd1;
     end else done <= 1'd0;
   end