Generate or-and trees for guarded assignments

[rachitnigam]

Instead of generating:

in = g0 ? o1 : 
       g1 ? o2 : 'x

This generates:

in = ({WIDTH{g0}} & o1) |
       ({WIDTH{g1}} & o2) | 0

Note that we have to generate 0 instead of 'x because otherwise the &-| chain will produce an 'x value.

The --emit-mux option simulates the old behavior.

I'm also noticing that a lot of optimizations around guards are now happening within the Verilog backend which is bad. We should move that logic into a pass if possible.

[rachitnigam]

Fixes #1423

[andrewb1999]

I think if/when this gets merged this should not be made the default yet. As mentioned on slack I have concerns that this will have unintended effects on resource utilization because it makes it harder for synthesis to optimize away guards.

[rachitnigam]

Good point! The alternative is generating casex statements which might not have the best support in the simulators we use but should otherwise support the optimization and generation of non-priority logic.

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