Multidimensional Memory in calyx-py #2240
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KabirSamsi
changed the title
| load_grp.done = reg.done | ||
| return load_grp | ||
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| def mem_latch_dn(self, mem, dims, indices, groupname): |
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I think if I'm understanding this correctly, this requires indices to be constants at compile-time. If so, it would be useful to add an assert to check that all the indices are in fact fact and throw an error if they are not.
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I presume you have a use-case for this! In general I think that an actual, say, 4D memory will be faster than your abstracted version. Is that fair @rachitnigam?
I have reviewed this for code quality etc., but you may also want to surface it on Zulip and ask what folks think! Unless of course you have a motivating example already.
| @@ -446,6 +446,24 @@ def comb_mem_d2( | |||
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| is_ref, | |||
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| def comb_mem_dn( | |||
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Consider a more descriptive name. dn reads like "down" to me! Also flesh out the docstring to explain what's up.
| self, | ||
| name: str, | ||
| bitwidth: int, | ||
| lens: List[int], |
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| lens: List[int], | |
| lengths: List[int], |
| @@ -482,6 +500,24 @@ def seq_mem_d2( | |||
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| def seq_mem_dn( | |||
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| name: str, | ||
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| lens : List[int], |
| @@ -898,6 +934,48 @@ def mem_latch_d2(self, mem, i, j, groupname): | |||
| latch_grp.done = mem.done | |||
| return latch_grp | |||
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| def flatten_idx(self, dims, indices): | |||
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| def mem_load_dn(self, mem, dims, indices, reg, groupname): | ||
| """Inserts wiring into `self` to perform `reg := mem[i1][i2]...[in]`, | ||
| where `mem` is a seq_dn memory or a comb_mem_d1 memory |
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Here, also explain the use-case of how indices has to be used. And consider the assertion that Rachit suggests below!
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@anshumanmohan when mapping onto hardware, there is no concept of multidimensional memories so the indexing logic will need to be generated by the synthesis tools (see #907); we are just making that explicit. I would suggest that in the case of power-of-two sizes, we generate optimized logic to compute the single-dimensional index that uses shift-right instead of multiplication. |
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Ah gotcha. And yes agreed that it would be good to exploit shifting when possible. Does this all make sense @KabirSamsi? Catch me in person if you’d like to discuss further :) |
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Thanks for the feedback – I think I follow! I'll follow up in-person with Anshuman to clarify. |
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Just a gentle nudge putting this back on your radar, @KabirSamsi. I think there are a couple concrete things to do here and then we can look at it again! |
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Oh my mistake, I thought we had put this on ice. I'll go through Rachit's advice and get back on this! |
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@KabirSamsi I'm going to go ahead and mark this as stale. If you're intending on working on this, please remove the tag and make the changes. Github will automatically close this PR in 7 days. |
This is a little abstraction that I thought could prove useful for the eDSL.
We have 1D memory and 2D memory, both in pure Calyx and in calyx-py. However, I thoguht it may be interesting to integrate multidimensional memories, provided there was a clean way to represent them in Calyx.
This version represents any 'n-d memory block' as a 1-dimensional memory cell, and introduces a simple Python function for translating a series of indices (e.g.
mem_rep[i][j][k]) into a corresponding index into the 1d representation. This support extends to both sequential and combinational memory.