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WIP: Create a backwards compatible flow for xo/xclbin generation with Calyx-AXI-wrapper #2267

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WIP: Create a backwards compatible flow for xo/xclbin generation with Calyx-AXI-wrapper #2267

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Commits on Jun 19, 2024

  1. add case statement support for ComponentBuilders

    @nathanielnrn
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  2. add runt tests

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Commits on Jun 20, 2024

  1. make channels for the subordinate controller

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  2. WIP: read controller. All channels exist

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  3. change case to return a par block instead of automatically adding to … 

    …control of a component
    @nathanielnrn
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  4. Merge branch 'case-statements' into xilinx-subordinate

    @nathanielnrn
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  5. WIP AXI subordinate controller 

    TODO: Hook up the slices in the highest level module for ap_done,
ap_start. Also thinnk about go done signals/how these connect to rest of
wrapper
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Commits on Jun 21, 2024

  1. Queues: use case statements in FIFO control (#2171) 

    * Prepare fifo for case idiom

* Attempt with . Failing due to empty control

* Delete calyx-py/test/correctness/queues/fifo.futil
    @anshumanmohan
    anshumanmohan authored Jun 21, 2024
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  2. improve naming of equalities and add name functions to some classes i… 

    …n builder
    @nathanielnrn
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  3. runt tests

    @nathanielnrn
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  4. Merge branch 'case-statements' of github.com:calyxir/calyx into case-… 

    …statements
    @nathanielnrn
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  5. apply black

    @nathanielnrn
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  6. Merge branch 'main' into case-statements

    @nathanielnrn
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  7. Merge branch 'case-statements' into xilinx-subordinate

    @nathanielnrn
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  8. remove extra print

    @nathanielnrn
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  9. runt tests

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  10. Merge branch 'main' into case-statements

    @nathanielnrn
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  11. Merge branch 'case-statements' into xilinx-subordinate

    @nathanielnrn
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  12. print out signals when possible for case statement signals

    @nathanielnrn
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  13. Merge branch 'case-statements' of github.com:calyxir/calyx into case-… 

    …statements
    @nathanielnrn
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  14. Merge branch 'case-statements' into xilinx-subordinate

    @nathanielnrn
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  15. might have working axi-controller. TODO: hoko up with overall wrapper

    @nathanielnrn
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  16. remove unused function from port attribute PR

    @nathanielnrn
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  17. Controller is largely done 

    TODO: Hook up ap_start from controller in wrapper to the main_compute
module
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Commits on Jun 24, 2024

  1. work on controller and hook up to dynamic axi

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Commits on Jul 9, 2024

  1. generator updates wip

    @nathanielnrn
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  2. fud2 update variable names

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Commits on Jul 11, 2024

  1. Add init invokes to ar,aw and w channels 

    This works around #2198 causing combinational loops
    @nathanielnrn
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  2. AddAXI manager to axi_test and writing to the control register

    @nathanielnrn
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Commits on Jul 14, 2024

  1. WIP do mnaual ref hoisting. Problem with signal names

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Commits on Jul 20, 2024

  1. wip on ref ports only assigning to ports actually used

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Commits on Jul 21, 2024

  1. WIP compile invoke only needed ports. TODO: add static assignments toowq

    @nathanielnrn
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  2. WIP: add static assignments to the limited ref assignments in groups

    @nathanielnrn
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  3. Update compile-invoke tests

    @nathanielnrn
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  4. Merge branch 'main' into limited-ref-ports

    @nathanielnrn
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  5. clippy and formatting

    @nathanielnrn
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  6. more formatting

    @nathanielnrn
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  7. update axi runt tests

    @nathanielnrn
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  8. Merge branch 'main' into xilinx-subordinate

    @nathanielnrn
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  9. Merge branch 'limited-ref-ports' into xilinx-subordinate

    @nathanielnrn
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  10. fud2 formatting

    @nathanielnrn
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  11. add writes to base addresses 

    (this means we need subordinate controller in all of our tests)
    @nathanielnrn
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  12. get rid of added debug statements

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Commits on Jul 22, 2024

  1. improve comments

    @nathanielnrn
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  2. Merge branch 'limited-ref-ports' into xilinx-subordinate

    @nathanielnrn
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  3. add nested while loops to subordinate controller 

    Hopefully models daemons.
    @nathanielnrn
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Commits on Jul 24, 2024

  1. Fix memory mapping addresses in axi_test 

    Also change how ap_done is handled in controller. It short circuits
off of the ap_done input instead of the control register output
    @nathanielnrn
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  2. thread through ap_done for early termination of all groups in the con… 

    …troller subordinate
    @nathanielnrn
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Commits on Jul 27, 2024

  1. rename axi_generator to use underscore

    @nathanielnrn
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  2. dynamic axi-generator typo

    @nathanielnrn
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  3. add an xml_generator from a .yxi file

    @nathanielnrn
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  4. add link to spec

    @nathanielnrn
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  5. revert name change axi_generator

    @nathanielnrn
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  6. runt tests for new xml generator

    @nathanielnrn
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Commits on Jul 31, 2024

  1. change gen_xo (in fud2 dir) toplevel from 'Toplevel' to 'wrapper'

    @nathanielnrn
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  2. simplify axi fud2 invocation

    @nathanielnrn
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  3. formatting in fud2/lib.rs

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Commits on Aug 1, 2024

  1. WIP to allow creation of .xo from calyx file using new calyx-axi-wrapper

    @nathanielnrn
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  2. Merge branch 'main' into xml-fud2

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  3. Merge branch 'xilinx-subordinate' into xml-fud2

    @nathanielnrn
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  4. wip get verilog to xo fud2 invocation working. TODO: Figure out why g… 

    …lob does not find any .v files
    @nathanielnrn
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  5. get vitis invocation to start correctly

    @nathanielnrn
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  6. change kernel root to expect 'wrapper' toplevel name instead of 'Topl… 

    …evel'. This generator will not work with the old verilog-wrapper
    @nathanielnrn
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  7. change gen_xo.tcl associate_bus_interface clock from 'ap_clk' to 'clk'

    @nathanielnrn
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  8. add a todo

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  9. remove stray merge conflict from lib.rs

    @nathanielnrn
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Commits on Aug 2, 2024

  1. channel reset to be driven by ap_rst_n

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  2. Merge branch 'xilinx-subordinate' into xml-fud2

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Commits on Aug 4, 2024

  1. xclrun: Remove timeout parameter 

    This is no longer an argument to our YXI-wrapped kernels; it only exists
in the old Verilog-generator stuff. We maybe want to revert/make this
optional at some point to make `xclrun` compatible with the old version
too?
    @sampsyo
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Commits on Aug 19, 2024

  1. Merge branch 'xml-fud2' of github.com:calyxir/calyx into xml-fud2

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  2. Merge branch 'main' into xilinx-subordinate

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  3. Merge branch 'xilinx-subordinate' into xml-fud2

    @nathanielnrn
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  4. update dynamic wrapper to use an ap_clk signal

    @nathanielnrn
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  5. Change axi wrapper output to maintain compatability 

    This allows us to not change the `kernel.xml` we use in the old wrapper
vs the new wrapper and still get correct results
    @nathanielnrn
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  6. Merge branch 'main' into limited-ref-ports

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  7. Merge branch 'limited-ref-ports' into xml-fud2

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Commits on Aug 20, 2024

  1. rename generated toplevel to 'Toplevel' for backwards compatibility w… 

    …ith verilog AXI wrapper
    @nathanielnrn
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  2. make cocotb testing dynamic w.r.t memory base address control registers

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  3. add calyx wrapper flag for calyx wrapped AXI runnign via xclrun

    @nathanielnrn
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  4. builder cleanup

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Commits on Aug 28, 2024

  1. rename wrapper to 'Toplevel'

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