Adding RISCV to supported architectures#83

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moste00 wants to merge 6 commits intocapstone-engine:auto-sync-18from

moste00:riscv_support

Commits on Jul 17, 2025

Added RISCV to supported architectures and added code to recognize its immediate operands
moste00
committed

Commits on Jul 26, 2025

added support for primary key index generation and other fixes
moste00
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Commits on Aug 23, 2025

added compressed instruction info generation and the necessary fixes
moste00
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Commits on Sep 5, 2025

final touches to fix the generation of compressed instruction info logic
moste00
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Commits on Oct 21, 2025

added isCall flag and generated MEM access for some instructions with missing MEM
moste00
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Commits on Oct 22, 2025

[BACKPATCH] fixed problem with c_srli immediates by cherry picking a fix from upstream, REMOVE WHEN REBASING ON TOP OF 20.0
moste00
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