refactor: unify different "reg" enums into one

src/i-virtual-machine.h

@@ -45,7 +45,7 @@ namespace cartesi {
 class i_virtual_machine {
 public:
     using hash_type = machine_merkle_tree::hash_type;
-    using reg = machine::reg;
+    using reg = machine_reg;
 
     /// \brief Constructor
     i_virtual_machine() = default;

src/machine-reg.h

@@ -0,0 +1,192 @@
+// Copyright Cartesi and individual authors (see AUTHORS)
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// This program is free software: you can redistribute it and/or modify it under
+// the terms of the GNU Lesser General Public License as published by the Free
+// Software Foundation, either version 3 of the License, or (at your option) any
+// later version.
+//
+// This program is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+// PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License along
+// with this program (see COPYING). If not, see <https://www.gnu.org/licenses/>.
+//
+
+#ifndef MACHINE_REG_H
+#define MACHINE_REG_H
+
+/// \file
+/// \brief Cartesi machine registers
+
+namespace cartesi {
+
+/// \brief List of machine registers
+enum class machine_reg {
+    // Processor x registers
+    first_ = 0,
+    x0 = first_,
+    x1,
+    x2,
+    x3,
+    x4,
+    x5,
+    x6,
+    x7,
+    x8,
+    x9,
+    x10,
+    x11,
+    x12,
+    x13,
+    x14,
+    x15,
+    x16,
+    x17,
+    x18,
+    x19,
+    x20,
+    x21,
+    x22,
+    x23,
+    x24,
+    x25,
+    x26,
+    x27,
+    x28,
+    x29,
+    x30,
+    x31,
+    // Processor f registers
+    f0,
+    f1,
+    f2,
+    f3,
+    f4,
+    f5,
+    f6,
+    f7,
+    f8,
+    f9,
+    f10,
+    f11,
+    f12,
+    f13,
+    f14,
+    f15,
+    f16,
+    f17,
+    f18,
+    f19,
+    f20,
+    f21,
+    f22,
+    f23,
+    f24,
+    f25,
+    f26,
+    f27,
+    f28,
+    f29,
+    f30,
+    f31,
+    // Processor CSRs
+    pc,
+    fcsr,
+    mvendorid,
+    marchid,
+    mimpid,
+    mcycle,
+    icycleinstret,
+    mstatus,
+    mtvec,
+    mscratch,
+    mepc,
+    mcause,
+    mtval,
+    misa,
+    mie,
+    mip,
+    medeleg,
+    mideleg,
+    mcounteren,
+    menvcfg,
+    stvec,
+    sscratch,
+    sepc,
+    scause,
+    stval,
+    satp,
+    scounteren,
+    senvcfg,
+    ilrsc,
+    iflags,
+    iunrep,
+    clint_mtimecmp,
+    plic_girqpend,
+    plic_girqsrvd,
+    htif_tohost,
+    htif_fromhost,
+    htif_ihalt,
+    htif_iconsole,
+    htif_iyield,
+    last_ = htif_iyield,
+    // Microarchitecture processor
+    uarch_first_,
+    uarch_x0 = uarch_first_,
+    uarch_x1,
+    uarch_x2,
+    uarch_x3,
+    uarch_x4,
+    uarch_x5,
+    uarch_x6,
+    uarch_x7,
+    uarch_x8,
+    uarch_x9,
+    uarch_x10,
+    uarch_x11,
+    uarch_x12,
+    uarch_x13,
+    uarch_x14,
+    uarch_x15,
+    uarch_x16,
+    uarch_x17,
+    uarch_x18,
+    uarch_x19,
+    uarch_x20,
+    uarch_x21,
+    uarch_x22,
+    uarch_x23,
+    uarch_x24,
+    uarch_x25,
+    uarch_x26,
+    uarch_x27,
+    uarch_x28,
+    uarch_x29,
+    uarch_x30,
+    uarch_x31,
+    uarch_pc,
+    uarch_cycle,
+    uarch_halt_flag,
+    uarch_last_ = uarch_halt_flag,
+    count_,
+    // Views of registers
+    iflags_prv,
+    iflags_x,
+    iflags_y,
+    iflags_h,
+    htif_tohost_dev,
+    htif_tohost_cmd,
+    htif_tohost_reason,
+    htif_tohost_data,
+    htif_fromhost_dev,
+    htif_fromhost_cmd,
+    htif_fromhost_reason,
+    htif_fromhost_data,
+    unknown_,
+};
+
+} // namespace cartesi
+
+#endif // MACHINE_REG_H