GitHub - chawl002/Verilog-MCU: Learning Verilog and Modelsim

Name		Name	Last commit message	Last commit date
Latest commit History 15 Commits
ALU.v		ALU.v
FSM.v		FSM.v
IR.v		IR.v
PC.v		PC.v
PCMUX.v		PCMUX.v
RAM.v		RAM.v
REGBANK.v		REGBANK.v
ROM.v		ROM.v
ZeroExtender.v		ZeroExtender.v
memory.txt		memory.txt

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Learning Verilog and Modelsim

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Verilog 100.0%