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constr/Basys3.xdc

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+
+# Clock signal
+#Bank = 34, Pin name = ,					Sch name = CLK100MHZ
+set_property PACKAGE_PIN W5 [get_ports CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports CLK]
+create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports CLK]
+
+# Switches
+set_property PACKAGE_PIN V17 [get_ports {SW[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[0]}]
+set_property PACKAGE_PIN V16 [get_ports {SW[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[1]}]
+set_property PACKAGE_PIN W16 [get_ports {SW[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[2]}]
+set_property PACKAGE_PIN W17 [get_ports {SW[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[3]}]
+set_property PACKAGE_PIN W15 [get_ports {SW[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[4]}]
+set_property PACKAGE_PIN V15 [get_ports {SW[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[5]}]
+set_property PACKAGE_PIN W14 [get_ports {SW[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[6]}]
+set_property PACKAGE_PIN W13 [get_ports {SW[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[7]}]
+set_property PACKAGE_PIN V2 [get_ports {SW[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[8]}]
+set_property PACKAGE_PIN T3 [get_ports {SW[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[9]}]
+set_property PACKAGE_PIN T2 [get_ports {SW[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[10]}]
+set_property PACKAGE_PIN R3 [get_ports {SW[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[11]}]
+set_property PACKAGE_PIN W2 [get_ports {SW[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[12]}]
+set_property PACKAGE_PIN U1 [get_ports {SW[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[13]}]
+set_property PACKAGE_PIN T1 [get_ports {SW[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[14]}]
+set_property PACKAGE_PIN R2 [get_ports {SW[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[15]}]
+
+# LEDs
+set_property PACKAGE_PIN U16 [get_ports {LED[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]
+set_property PACKAGE_PIN E19 [get_ports {LED[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}]
+set_property PACKAGE_PIN U19 [get_ports {LED[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}]
+set_property PACKAGE_PIN V19 [get_ports {LED[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}]
+set_property PACKAGE_PIN U16 [get_ports {LED[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]
+set_property PACKAGE_PIN E19 [get_ports {LED[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}]
+set_property PACKAGE_PIN U19 [get_ports {LED[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}]
+set_property PACKAGE_PIN V19 [get_ports {LED[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}]
+set_property PACKAGE_PIN W18 [get_ports {LED[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[4]}]
+set_property PACKAGE_PIN U15 [get_ports {LED[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[5]}]
+set_property PACKAGE_PIN U14 [get_ports {LED[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[6]}]
+set_property PACKAGE_PIN V14 [get_ports {LED[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}]
+set_property PACKAGE_PIN V13 [get_ports {LED[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[8]}]
+set_property PACKAGE_PIN V3 [get_ports {LED[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[9]}]
+set_property PACKAGE_PIN W3 [get_ports {LED[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[10]}]
+set_property PACKAGE_PIN U3 [get_ports {LED[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[11]}]
+set_property PACKAGE_PIN P3 [get_ports {LED[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[12]}]
+set_property PACKAGE_PIN N3 [get_ports {LED[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[13]}]
+set_property PACKAGE_PIN P1 [get_ports {LED[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[14]}]
+set_property PACKAGE_PIN L1 [get_ports {LED[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[15]}]
+
+
+#7 segment display
+#Bank = 34, Pin name = ,						Sch name = CA
+set_property PACKAGE_PIN W7 [get_ports {SSEG_CA[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_CA[0]}]
+#Bank = 34, Pin name = ,					Sch name = CB
+set_property PACKAGE_PIN W6 [get_ports {SSEG_CA[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_CA[1]}]
+#Bank = 34, Pin name = ,					Sch name = CC
+set_property PACKAGE_PIN U8 [get_ports {SSEG_CA[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_CA[2]}]
+#Bank = 34, Pin name = ,						Sch name = CD
+set_property PACKAGE_PIN V8 [get_ports {SSEG_CA[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_CA[3]}]
+#Bank = 34, Pin name = ,						Sch name = CE
+set_property PACKAGE_PIN U5 [get_ports {SSEG_CA[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_CA[4]}]
+#Bank = 34, Pin name = ,						Sch name = CF
+set_property PACKAGE_PIN V5 [get_ports {SSEG_CA[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_CA[5]}]
+#Bank = 34, Pin name = ,						Sch name = CG
+set_property PACKAGE_PIN U7 [get_ports {SSEG_CA[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_CA[6]}]
+
+#Bank = 34, Pin name = ,						Sch name = DP
+set_property PACKAGE_PIN V7 [get_ports {SSEG_CA[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_CA[7]}]
+
+#Bank = 34, Pin name = ,						Sch name = AN0
+set_property PACKAGE_PIN U2 [get_ports {SSEG_AN[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_AN[0]}]
+#Bank = 34, Pin name = ,						Sch name = AN1
+set_property PACKAGE_PIN U4 [get_ports {SSEG_AN[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_AN[1]}]
+#Bank = 34, Pin name = ,						Sch name = AN2
+set_property PACKAGE_PIN V4 [get_ports {SSEG_AN[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_AN[2]}]
+#Bank = 34, Pin name = ,					Sch name = AN3
+set_property PACKAGE_PIN W4 [get_ports {SSEG_AN[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_AN[3]}]
+
+
+
+# Timing
+set_false_path -from [get_ports {SW*}]
+set_false_path -to [get_ports {LED*}]
+set_false_path -to [get_ports {SSEG_CA*}]
+set_false_path -to [get_ports {SSEG_AN*}]
+
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]
+
+set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+
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