First release of VHDL saturation counter

These folders include the implementation and simulation of a generic saturation counter in VHDL.
A saturation counters counts from 0 to (saturation value)-1.
When the counter reaches the value (saturation value)-1 it stays at that value for any additional count-up command until the 'sclr' signal is asserted.

The saturation value and the counter width are parameters of the VHDL component

This release includes:

VHDL source file
Test Bench sources
Modelsim Altera project file
Wave.do for modelsim
Captured waveforms