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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 [email protected]

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

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  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

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  2. rocket-chip rocket-chip Public

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  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

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  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

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  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

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  6. firrtl firrtl Public

    Flexible Intermediate Representation for RTL

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Repositories

Showing 10 of 97 repositories
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 3,804 Apache-2.0 574 302 (1 issue needs help) 151 Updated Jun 28, 2024
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 48 Apache-2.0 34 70 77 Updated Jun 28, 2024
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2’s past year of commit activity
    SystemVerilog 231 Apache-2.0 68 28 15 Updated Jun 28, 2024
  • riscv-dv Public

    Random instruction generator for RISC-V processor verification

    chipsalliance/riscv-dv’s past year of commit activity
    Python 970 Apache-2.0 312 110 11 Updated Jun 28, 2024
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 92 Apache-2.0 19 14 10 Updated Jun 28, 2024
  • synlig-logs Public
    chipsalliance/synlig-logs’s past year of commit activity
    0 0 0 0 Updated Jun 28, 2024
  • synlig Public

    SystemVerilog support for Yosys

    chipsalliance/synlig’s past year of commit activity
    Verilog 144 Apache-2.0 20 84 13 Updated Jun 28, 2024
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 5 1 0 0 Updated Jun 28, 2024
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator’s past year of commit activity
    C++ 33 LGPL-3.0 559 0 1 Updated Jun 28, 2024
  • f4pga Public

    FOSS Flow For FPGA

    chipsalliance/f4pga’s past year of commit activity
    Python 333 Apache-2.0 45 13 12 Updated Jun 28, 2024
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