Sync code with caliptra-rtl repo #182

koblonczek · 2024-06-07T12:53:01Z

This PR brings partial changes from caliptra-rtl repo that have happened since the last code sync. These include:

lint changes
exposing jtag_tdoEn in el2_veer_wrapper (fixes Caliptra JTAG TdoEn missing output #159)

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

design/lsu/el2_lsu_bus_intf.sv|262|
design/lsu/el2_lsu_dccm_mem.sv|57|
design/lsu/el2_lsu_lsc_ctl.sv|301|
design/lsu/el2_lsu_lsc_ctl.sv|304|
design/lsu/el2_lsu_lsc_ctl.sv|307|
design/lsu/el2_lsu_trigger.sv|56|

design/dec/el2_dec_decode_ctl.sv

design/dec/el2_dec_tlu_ctl.sv

design/lsu/el2_lsu_addrcheck.sv

design/lsu/el2_lsu_bus_buffer.sv

design/lsu/el2_lsu_bus_intf.sv

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-lint

design/exu/el2_exu_mul_ctl.sv|526 col 101| Line length exceeds max: 100; is: 167 [Style: line-length] [line-length]
design/exu/el2_exu_mul_ctl.sv|527 col 101| Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
design/exu/el2_exu_mul_ctl.sv|528 col 101| Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
design/exu/el2_exu_mul_ctl.sv|529 col 101| Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
design/exu/el2_exu_mul_ctl.sv|530 col 101| Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
design/exu/el2_exu_mul_ctl.sv|531 col 101| Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
design/exu/el2_exu_mul_ctl.sv|532 col 101| Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
design/exu/el2_exu_mul_ctl.sv|533 col 101| Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
design/exu/el2_exu_mul_ctl.sv|535 col 101| Line length exceeds max: 100; is: 167 [Style: line-length] [line-length]
design/exu/el2_exu_mul_ctl.sv|536 col 101| Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
design/exu/el2_exu_mul_ctl.sv|537 col 101| Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
design/exu/el2_exu_mul_ctl.sv|538 col 101| Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
design/exu/el2_exu_mul_ctl.sv|540 col 101| Line length exceeds max: 100; is: 168 [Style: line-length] [line-length]
design/exu/el2_exu_mul_ctl.sv|541 col 101| Line length exceeds max: 100; is: 122 [Style: line-length] [line-length]
design/lsu/el2_lsu_trigger.sv|56 col 39| All generate block labels must start with g_ or gen_ [Style: generate-constructs] [generate-label-prefix]
design/ifu/el2_ifu_ifc_ctl.sv|104 col 30| All generate block labels must start with g_ or gen_ [Style: generate-constructs] [generate-label-prefix]
design/ifu/el2_ifu_ifc_ctl.sv|129 col 68| Binary literal 30'b1 has less digits than expected for 30 bits. [Style: number-literals] [undersized-binary-literal]
design/ifu/el2_ifu_ifc_ctl.sv|217 col 31| All generate block labels must start with g_ or gen_ [Style: generate-constructs] [generate-label-prefix]

design/ifu/el2_ifu_aln_ctl.sv

design/dec/el2_dec_trigger.sv

design/lib/beh_lib.sv

design/lsu/el2_lsu_dccm_mem.sv

* Resolving unnamed generate blocks Lint warnings * Running stamp_repo.sh --------- Co-authored-by: Avirup Mullick <[email protected]>

github-actions · 2024-06-20T16:05:05Z

design/ifu/el2_ifu_ifc_ctl.sv

@@ -101,7 +101,7 @@ import el2_pkg::*;
   // - Miss *or* flush during WFM (icache miss buffer is blocking)
   // - Sequential

-if(pt.BTB_ENABLE==1) begin
+if(pt.BTB_ENABLE==1) begin : genblock1


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
All generate block labels must start with g_ or gen_ [Style: generate-constructs] [generate-label-prefix]

github-actions · 2024-06-20T16:05:05Z

design/ifu/el2_ifu_ifc_ctl.sv

+   assign fetch_addr_next[31:1] = {({ifc_fetch_addr_f[31:2]} + 30'b1), fetch_addr_next_1 };
   assign line_wrap = (fetch_addr_next[pt.ICACHE_TAG_INDEX_LO] ^ ifc_fetch_addr_f[pt.ICACHE_TAG_INDEX_LO]);


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Binary literal 30'b1 has less digits than expected for 30 bits. [Style: number-literals] [undersized-binary-literal]

Suggested change

assign fetch_addr_next[31:1] = {({ifc_fetch_addr_f[31:2]} + 30'b1), fetch_addr_next_1 };

assign line_wrap = (fetch_addr_next[pt.ICACHE_TAG_INDEX_LO] ^ ifc_fetch_addr_f[pt.ICACHE_TAG_INDEX_LO]);

assign fetch_addr_next[31:1] = {({ifc_fetch_addr_f[31:2]} + 30'b assign fetch_addr_next[31:1] = {({ifc_fetch_addr_f[31:2]} + 30'b000000000000000000000000000001), fetch_addr_next_1 };

assign line_wrap = (fetch_addr_next[pt.ICACHE_TAG_INDEX_LO] ^ ifc_fetch_addr_f[pt.ICACHE_TAG_INDEX_LO]);

github-actions · 2024-06-20T16:05:05Z

design/ifu/el2_ifu_ifc_ctl.sv

@@ -214,7 +214,7 @@
   rvdffpcie #(31) faddrf1_ff  (.*, .en(fetch_bf_en), .din(fetch_addr_bf[31:1]), .dout(ifc_fetch_addr_f[31:1]));


- if (pt.ICCM_ENABLE)  begin
+ if (pt.ICCM_ENABLE)  begin : genblock2


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
All generate block labels must start with g_ or gen_ [Style: generate-constructs] [generate-label-prefix]

github-actions · 2024-06-20T16:05:05Z

design/exu/el2_exu_mul_ctl.sv

-
-   assign xperm_h[15:00]         =  {16{ ~(| rs2_in[15:01]) }} & ( (rs1_in[31:0] >> {rs2_in[00]   ,4'b0}) & 16'hffff );   // This is a 2:1 mux with qualified selects
-   assign xperm_h[31:16]         =  {16{ ~(| rs2_in[31:17]) }} & ( (rs1_in[31:0] >> {rs2_in[16]   ,4'b0}) & 16'hffff );
+   assign xperm_n[03:00]         =  { 4{    ~rs2_in[03]     }} & 4'( (rs1_in[31:0] >> {rs2_in[02:00],2'b0}) &     4'hf );   // This is a 8:1 mux with qualified selects


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 167 [Style: line-length] [line-length]

github-actions · 2024-06-20T16:05:06Z

design/exu/el2_exu_mul_ctl.sv

-   assign xperm_h[15:00]         =  {16{ ~(| rs2_in[15:01]) }} & ( (rs1_in[31:0] >> {rs2_in[00]   ,4'b0}) & 16'hffff );   // This is a 2:1 mux with qualified selects
-   assign xperm_h[31:16]         =  {16{ ~(| rs2_in[31:17]) }} & ( (rs1_in[31:0] >> {rs2_in[16]   ,4'b0}) & 16'hffff );
+   assign xperm_n[03:00]         =  { 4{    ~rs2_in[03]     }} & 4'( (rs1_in[31:0] >> {rs2_in[02:00],2'b0}) &     4'hf );   // This is a 8:1 mux with qualified selects
+   assign xperm_n[07:04]         =  { 4{    ~rs2_in[07]     }} & 4'( (rs1_in[31:0] >> {rs2_in[06:04],2'b0}) &     4'hf );


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]

github-actions · 2024-06-20T16:05:06Z

design/exu/el2_exu_mul_ctl.sv

+
+   assign xperm_b[07:00]         =  { 8{ ~(| rs2_in[07:02]) }} & 8'( (rs1_in[31:0] >> {rs2_in[01:00],3'b0}) &    8'hff );   // This is a 4:1 mux with qualified selects
+   assign xperm_b[15:08]         =  { 8{ ~(| rs2_in[15:10]) }} & 8'( (rs1_in[31:0] >> {rs2_in[09:08],3'b0}) &    8'hff );
+   assign xperm_b[23:16]         =  { 8{ ~(| rs2_in[23:18]) }} & 8'( (rs1_in[31:0] >> {rs2_in[17:16],3'b0}) &    8'hff );


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]

github-actions · 2024-06-20T16:05:06Z

design/exu/el2_exu_mul_ctl.sv

+   assign xperm_b[07:00]         =  { 8{ ~(| rs2_in[07:02]) }} & 8'( (rs1_in[31:0] >> {rs2_in[01:00],3'b0}) &    8'hff );   // This is a 4:1 mux with qualified selects
+   assign xperm_b[15:08]         =  { 8{ ~(| rs2_in[15:10]) }} & 8'( (rs1_in[31:0] >> {rs2_in[09:08],3'b0}) &    8'hff );
+   assign xperm_b[23:16]         =  { 8{ ~(| rs2_in[23:18]) }} & 8'( (rs1_in[31:0] >> {rs2_in[17:16],3'b0}) &    8'hff );
+   assign xperm_b[31:24]         =  { 8{ ~(| rs2_in[31:26]) }} & 8'( (rs1_in[31:0] >> {rs2_in[25:24],3'b0}) &    8'hff );


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]

github-actions · 2024-06-20T16:05:06Z

design/exu/el2_exu_mul_ctl.sv

+   assign xperm_b[23:16]         =  { 8{ ~(| rs2_in[23:18]) }} & 8'( (rs1_in[31:0] >> {rs2_in[17:16],3'b0}) &    8'hff );
+   assign xperm_b[31:24]         =  { 8{ ~(| rs2_in[31:26]) }} & 8'( (rs1_in[31:0] >> {rs2_in[25:24],3'b0}) &    8'hff );
+
+   assign xperm_h[15:00]         =  {16{ ~(| rs2_in[15:01]) }} & 16'( (rs1_in[31:0] >> {rs2_in[00]   ,4'b0}) & 16'hffff );   // This is a 2:1 mux with qualified selects


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 168 [Style: line-length] [line-length]

github-actions · 2024-06-20T16:05:06Z

design/exu/el2_exu_mul_ctl.sv

+   assign xperm_b[31:24]         =  { 8{ ~(| rs2_in[31:26]) }} & 8'( (rs1_in[31:0] >> {rs2_in[25:24],3'b0}) &    8'hff );
+
+   assign xperm_h[15:00]         =  {16{ ~(| rs2_in[15:01]) }} & 16'( (rs1_in[31:0] >> {rs2_in[00]   ,4'b0}) & 16'hffff );   // This is a 2:1 mux with qualified selects
+   assign xperm_h[31:16]         =  {16{ ~(| rs2_in[31:17]) }} & 16'( (rs1_in[31:0] >> {rs2_in[16]   ,4'b0}) & 16'hffff );


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 122 [Style: line-length] [line-length]

github-actions · 2024-06-20T16:05:07Z

design/lsu/el2_lsu_trigger.sv

@@ -53,7 +53,7 @@ import el2_pkg::*;
   assign ldst_addr_trigger_m[31:0]  = lsu_addr_m[31:0] & {32{trigger_enable}};


-   for (genvar i=0; i<4; i++) begin
+   for (genvar i=0; i<4; i++) begin : genblock


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
All generate block labels must start with g_ or gen_ [Style: generate-constructs] [generate-label-prefix]

github-actions · 2024-06-20T16:05:09Z

design/lsu/el2_lsu_bus_intf.sv

@@ -256,7 +256,7 @@ import el2_pkg::*;
   // This will be high if all the bytes of load hit the stores in pipe/write buffer (m/r/wrbuf)
   assign ld_full_hit_m = ld_full_hit_lo_m & ld_full_hit_hi_m & lsu_busreq_m & lsu_pkt_m.load & ~is_sideeffects_m;

-   assign ld_fwddata_m[63:0] = {ld_fwddata_hi[31:0], ld_fwddata_lo[31:0]} >> (8*lsu_addr_m[1:0]);
+   assign ld_fwddata_m[63:0] = 64'({ld_fwddata_hi[31:0], ld_fwddata_lo[31:0]} >> (8*lsu_addr_m[1:0]));
   assign bus_read_data_m[31:0]                        = ld_fwddata_m[31:0];

   // Fifo flops


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Fifo flops

assign ld_fwddata_m[63:0] = 64'({ld_fwddata_hi[31:0], ld_fwddata_lo[31:0]} >> (8*lsu_addr_m[1:0]));

assign bus_read_data_m[31:0] = ld_fwddata_m[31:0];

github-actions · 2024-06-20T16:05:09Z

design/lsu/el2_lsu_dccm_mem.sv

+   localparam logic [5:0]  DCCM_WIDTH_BITS = $clog2(pt.DCCM_BYTE_WIDTH);
+   localparam logic [7:0]  DCCM_INDEX_BITS = 8'(pt.DCCM_BITS - pt.DCCM_BANK_BITS - pt.DCCM_WIDTH_BITS);
+   localparam logic [31:0] DCCM_INDEX_DEPTH = ((pt.DCCM_SIZE)*1024)/((pt.DCCM_BYTE_WIDTH)*(pt.DCCM_NUM_BANKS));  // Depth of memory bank


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

localparam logic [5:0] DCCM_WIDTH_BITS = $clog2(pt.DCCM_BYTE_WIDTH);

localparam logic [7:0] DCCM_INDEX_BITS = 8'(pt.DCCM_BITS - pt.DCCM_BANK_BITS - pt.DCCM_WIDTH_BITS);

localparam logic [31:0] DCCM_INDEX_DEPTH = ((pt.DCCM_SIZE)*1024)/((pt.DCCM_BYTE_WIDTH)*(pt.DCCM_NUM_BANKS)); // Depth of memory bank

localparam logic [5:0] DCCM_WIDTH_BITS = $clog2(pt.DCCM_BYTE_WIDTH);

localparam logic [7:0] DCCM_INDEX_BITS = 8'(pt.DCCM_BITS - pt.DCCM_BANK_BITS - pt.DCCM_WIDTH_BITS);

localparam logic [31:0] DCCM_INDEX_DEPTH = ((pt.DCCM_SIZE)*1024)/((pt.DCCM_BYTE_WIDTH)*(pt.DCCM_NUM_BANKS)); // Depth of memory bank

github-actions · 2024-06-20T16:05:09Z

design/lsu/el2_lsu_lsc_ctl.sv

   // Interrupt as a flush source allows the WB to occur
   assign lsu_commit_r = lsu_pkt_r.valid & (lsu_pkt_r.store | lsu_pkt_r.load) & ~flush_r & ~lsu_pkt_r.dma;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// Interrupt as a flush source allows the WB to occur

assign lsu_commit_r = lsu_pkt_r.valid & (lsu_pkt_r.store | lsu_pkt_r.load) & ~flush_r & ~lsu_pkt_r.dma;

// Interrupt as a flush source allows the WB to occur

assign lsu_commit_r = lsu_pkt_r.valid & (lsu_pkt_r.store | lsu_pkt_r.load) & ~flush_r & ~lsu_pkt_r.dma;

github-actions · 2024-06-20T16:05:09Z

design/lsu/el2_lsu_lsc_ctl.sv

+   assign dma_mem_wdata_shifted[63:0] = 64'(dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000});   // Shift the dma data to lower bits to make it consistent to lsu stores
   assign store_data_d[31:0] = dma_dccm_req ? dma_mem_wdata_shifted[31:0] : exu_lsu_rs2_d[31:0];  // Write to PIC still happens in r stage


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign dma_mem_wdata_shifted[63:0] = 64'(dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000}); // Shift the dma data to lower bits to make it consistent to lsu stores

assign store_data_d[31:0] = dma_dccm_req ? dma_mem_wdata_shifted[31:0] : exu_lsu_rs2_d[31:0]; // Write to PIC still happens in r stage

assign dma_mem_wdata_shifted[63:0] = 64'(dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000}); // Shift the dma data to lower bits to make it consistent to lsu stores

assign store_data_d[31:0] = dma_dccm_req ? dma_mem_wdata_shifted[31:0] : exu_lsu_rs2_d[31:0]; // Write to PIC still happens in r stage

github-actions · 2024-06-20T16:05:09Z

design/lsu/el2_lsu_lsc_ctl.sv

@@ -301,7 +301,7 @@
   // Interrupt as a flush source allows the WB to occur
   assign lsu_commit_r = lsu_pkt_r.valid & (lsu_pkt_r.store | lsu_pkt_r.load) & ~flush_r & ~lsu_pkt_r.dma;

-   assign dma_mem_wdata_shifted[63:0] = dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000};   // Shift the dma data to lower bits to make it consistent to lsu stores
+   assign dma_mem_wdata_shifted[63:0] = 64'(dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000});   // Shift the dma data to lower bits to make it consistent to lsu stores
   assign store_data_d[31:0] = dma_dccm_req ? dma_mem_wdata_shifted[31:0] : exu_lsu_rs2_d[31:0];  // Write to PIC still happens in r stage

   assign store_data_m_in[31:0] = (lsu_pkt_d.store_data_bypass_d) ? lsu_result_m[31:0] : store_data_d[31:0];


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign store_data_m_in[31:0] = (lsu_pkt_d.store_data_bypass_d) ? lsu_result_m[31:0] : store_data_d[31:0];

assign store_data_m_in[31:0] = (lsu_pkt_d.store_data_bypass_d) ? lsu_result_m[31:0] : store_data_d[31:0];

github-actions · 2024-06-20T16:05:09Z

design/lsu/el2_lsu_trigger.sv

+   for (genvar i=0; i<4; i++) begin : genblock
      assign lsu_match_data[i][31:0] = ({32{~trigger_pkt_any[i].select}} & ldst_addr_trigger_m[31:0]) |


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

for (genvar i=0; i<4; i++) begin : genblock

assign lsu_match_data[i][31:0] = ({32{~trigger_pkt_any[i].select}} & ldst_addr_trigger_m[31:0]) |

for (genvar i = 0; i < 4; i++) begin : genblock

assign lsu_match_data[i][31:0] = ({32{~trigger_pkt_any[i].select}} & ldst_addr_trigger_m[31:0]) |

github-actions · 2024-06-26T17:55:57Z

Links to coverage and verification reports for this PR (#182) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-07-01T11:25:23Z

design/ifu/el2_ifu_mem_ctl.sv

+                                 | ACCESS5_okay
+                                 | ACCESS6_okay
+                                 | ACCESS7_okay
+                               ;
   end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end

end

github-actions · 2024-07-01T11:25:23Z

design/ifu/el2_ifu_mem_ctl.sv

-
-
-
+   assign ifc_region_acc_fault_memory_bf = ~ifc_iccm_access_bf & ~ifc_region_acc_okay & ifc_fetch_req_bf;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign ifc_region_acc_fault_memory_bf = ~ifc_iccm_access_bf & ~ifc_region_acc_okay & ifc_fetch_req_bf;

assign ifc_region_acc_fault_memory_bf = ~ifc_iccm_access_bf & ~ifc_region_acc_okay & ifc_fetch_req_bf;

github-actions · 2024-07-01T12:14:01Z

design/ifu/el2_ifu_mem_ctl.sv

+                                 | ACCESS6_okay
+                                 | ACCESS7_okay
+                               ;
+
      assign ifc_region_acc_fault_memory_bf = ~ifc_iccm_access_bf & ~ifc_region_acc_okay & ifc_fetch_req_bf;
   end

   assign ifc_region_acc_fault_final_bf = ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign ifc_region_acc_fault_final_bf = ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf;

assign ifc_region_acc_fault_final_bf = ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf;

* Issue 445 LINT fixes * initial round of lint fixes * removing lint blackboxes removed packed struct post processing from generated reg files. cast width of dynamic shifts to make lint happy casting some arithmetic widths, math parameter widths etc * removing change from other lint pr branch, not sure where it came from. * fixing lint errors from LMS changes * rolling back packed struct removal enabling lint on integrated TRNG files fixes for integrated TRNG lint violations * updating reg files with latest version of reg gen * fixing script so it detects endpackage correctly * scrubbing enums in generated reg pkg files * NVDA Lint Fixes on top of main_lint_regress branch * matching number of bits on RHS of AND mask equation * Rename uses of keywords 'NULL', 'WAIT', 'Wait' * Cast address offset (constant) to addr_width for lint * Explicit types for localparams in VeeR * Change localparam types from 2-state to 4-state logic in csrng * Add 'unsigned' qualifier * Convert more localparam int to localparam logic [31:0] * Change module params from 2-state to 4-state logic in csrng * Cast a 33-bit expression as 32-bit (drop the carry bit) * Cast literal constant as unsigned for lint * rolling back change to modport to adhere to SV spec * fix to dmi reg data width lint violation * Regenerated reg macro files without ending newline * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/lint_fix' with updated timestamp and hash after successful run --------- Co-authored-by: Matthew Border <[email protected]> Co-authored-by: Michael Norris <[email protected]> Co-authored-by: Avirup Mullick <[email protected]> Co-authored-by: Michael Norris <[email protected]> Co-authored-by: Caleb Whitehead <[email protected]>

* porting tdo enable from jtag controller up to top level interface * updating top level testbench for uvm --------- Co-authored-by: Michael Norris <[email protected]>

Internal-tag: [#59554]

github-actions · 2024-07-02T08:15:56Z

Links to coverage and verification reports for this PR (#182) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions bot reviewed Jun 7, 2024

View reviewed changes

[LINT] Resolving unnamed generate blocks Lint warnings (#510)

2af62fd

* Resolving unnamed generate blocks Lint warnings * Running stamp_repo.sh --------- Co-authored-by: Avirup Mullick <[email protected]>

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github-actions bot reviewed Jun 20, 2024

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kiryk force-pushed the 59554-caliptra-sync-handpicked branch 4 times, most recently from 71aa60b to 2af62fd Compare June 26, 2024 16:48

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kiryk force-pushed the 59554-caliptra-sync-handpicked branch from 2a0a332 to 5933646 Compare July 1, 2024 12:13

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Nitsirks and others added 2 commits July 1, 2024 15:08

User/dev/michnorris/jtag port fix main (#425)

6b860db

* porting tdo enable from jtag controller up to top level interface * updating top level testbench for uvm --------- Co-authored-by: Michael Norris <[email protected]>

kiryk force-pushed the 59554-caliptra-sync-handpicked branch from 5933646 to c98a686 Compare July 1, 2024 13:09

Add missing pin

41f597e

Internal-tag: [#59554]

kiryk force-pushed the 59554-caliptra-sync-handpicked branch from c98a686 to 41f597e Compare July 2, 2024 07:12

kgugala merged commit 1106de8 into chipsalliance:main Jul 3, 2024
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kgugala deleted the 59554-caliptra-sync-handpicked branch July 3, 2024 10:48

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Sync code with caliptra-rtl repo #182

Sync code with caliptra-rtl repo #182

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		assign fetch_addr_next[31:1] = {({ifc_fetch_addr_f[31:2]} + 30'b1), fetch_addr_next_1 };
		assign line_wrap = (fetch_addr_next[pt.ICACHE_TAG_INDEX_LO] ^ ifc_fetch_addr_f[pt.ICACHE_TAG_INDEX_LO]);

	// Fifo flops
	assign ld_fwddata_m[63:0] = 64'({ld_fwddata_hi[31:0], ld_fwddata_lo[31:0]} >> (8*lsu_addr_m[1:0]));
	assign bus_read_data_m[31:0] = ld_fwddata_m[31:0];

		// Interrupt as a flush source allows the WB to occur
		assign lsu_commit_r = lsu_pkt_r.valid & (lsu_pkt_r.store \| lsu_pkt_r.load) & ~flush_r & ~lsu_pkt_r.dma;

		assign dma_mem_wdata_shifted[63:0] = 64'(dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000}); // Shift the dma data to lower bits to make it consistent to lsu stores
		assign store_data_d[31:0] = dma_dccm_req ? dma_mem_wdata_shifted[31:0] : exu_lsu_rs2_d[31:0]; // Write to PIC still happens in r stage

	assign store_data_m_in[31:0] = (lsu_pkt_d.store_data_bypass_d) ? lsu_result_m[31:0] : store_data_d[31:0];
	assign store_data_m_in[31:0] = (lsu_pkt_d.store_data_bypass_d) ? lsu_result_m[31:0] : store_data_d[31:0];

		for (genvar i=0; i<4; i++) begin : genblock
		assign lsu_match_data[i][31:0] = ({32{~trigger_pkt_any[i].select}} & ldst_addr_trigger_m[31:0]) \|




		assign ifc_region_acc_fault_memory_bf = ~ifc_iccm_access_bf & ~ifc_region_acc_okay & ifc_fetch_req_bf;

	assign ifc_region_acc_fault_final_bf = ifc_region_acc_fault_bf \| ifc_region_acc_fault_memory_bf;
	assign ifc_region_acc_fault_final_bf = ifc_region_acc_fault_bf \| ifc_region_acc_fault_memory_bf;

Sync code with caliptra-rtl repo #182

Sync code with caliptra-rtl repo #182

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