Wrong Parameter calculation in the elaborated model #3960
Comments
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@Pietro4F , please add a test that is a complete Verilog file (That at least parses and compile, even if it is minimal). Not just snippet of code. |
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I think the problem is just the it can't recognize the number with _ , for example It probably counts the 1_000_000 in the division as just 1, the same for 8_000_000. module abc #(
parameter A = 8_000_000,
parameter B = 100
)(
input wire clk,
input wire rst
);
localparam C = B * (A / 1_000_000);
endmodule
module top (
input wire clk,
input wire rst
);
abc #( .A(8_000_000), .B(100) ) u_abc (
.clk(clk),
.rst(rst)
);
endmoduleIn this first case C has the correct value only because A has the value of 8. Instead if I change from 8_000_000 to 8000000 I obtain C = 8000000 module abc #(
parameter A = 8_000_000,
parameter B = 100
)(
input wire clk,
input wire rst
);
localparam C = B * (A / 1_000_000);
endmodule
module top (
input wire clk,
input wire rst
);
abc #( .A(8000000), .B(100) ) u_abc (
.clk(clk),
.rst(rst)
);
endmodule |
|
Fixed in #3962 |
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Hello,
I've notice an error in the calculation of a parameter in the elaborated model.
I have different files with different modules, one of them is similar to this...
In the not elaborated tree i have this
But the in the elaborated tree i obtain 800000000 instead 800.
During the inclusion a give to the parameters the same values ad the default ones.
I have tried the same thing but with one simple module in one file.
So my module in that case is not included anywhere and I can obtain the correct result 800.
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