Review reset sequencing in verilator and FPGA models

[jhand2]

According to the integration spec cptra_rst and cptra_pwrgood should be synchronized with the Caliptra clock. Also this table indicates that cptra_powergood and cptra_rst should be deasserted on the same clock cycle.

This is likely not possible in the FPGA model because we do not have hardware that can drive those signals synchronized with the clock. So it makes sense that we deassert cptra_rst first to make sure it is already deasserting.

However in verilator we have fine-grained control over the clock. So we should make sure boot works as expected if both signals are deasserted on the same clock cycle.