Added cmake toolchain for RISC-V with clang.

- Added cross compile cmake file for target riscv64-clang
- Extended cmake for RISC-V and added instruction checks
- Created intrin_rvv.hpp with C++ version universal intrinsics

cmake/OpenCVCompilerOptimizations.cmake

@@ -49,6 +49,7 @@ list(APPEND CPU_ALL_OPTIMIZATIONS "AVX512_COMMON;AVX512_KNL;AVX512_KNM;AVX512_SK
 list(APPEND CPU_ALL_OPTIMIZATIONS NEON VFPV3 FP16)
 list(APPEND CPU_ALL_OPTIMIZATIONS MSA)
 list(APPEND CPU_ALL_OPTIMIZATIONS VSX VSX3)
+list(APPEND CPU_ALL_OPTIMIZATIONS RVV)
 list(REMOVE_DUPLICATES CPU_ALL_OPTIMIZATIONS)
 
 ocv_update(CPU_VFPV3_FEATURE_ALIAS "")
@@ -102,6 +103,8 @@ ocv_optimization_process_obsolete_option(ENABLE_NEON NEON OFF)
 
 ocv_optimization_process_obsolete_option(ENABLE_VSX VSX ON)
 
+ocv_optimization_process_obsolete_option(ENABLE_RVV RVV OFF)
+
 macro(ocv_is_optimization_in_list resultvar check_opt)
   set(__checked "")
   set(__queue ${ARGN})
@@ -366,6 +369,14 @@ elseif(PPC64LE)
 
   set(CPU_DISPATCH "VSX3" CACHE STRING "${HELP_CPU_DISPATCH}")
   set(CPU_BASELINE "VSX" CACHE STRING "${HELP_CPU_BASELINE}")
+
+elseif(RISCV)
+  ocv_update(CPU_RVV_TEST_FILE "${OpenCV_SOURCE_DIR}/cmake/checks/cpu_rvv.cpp")
+  ocv_update(CPU_KNOWN_OPTIMIZATIONS "RVV")
+  ocv_update(CPU_RVV_FLAGS_ON "")
+  set(CPU_DISPATCH "RVV" CACHE STRING "${HELP_CPU_DISPATCH}")
+  set(CPU_BASELINE "RVV" CACHE STRING "${HELP_CPU_BASELINE}")
+
 endif()
 
 # Helper values for cmake-gui

cmake/checks/cpu_rvv.cpp

@@ -0,0 +1,23 @@
+#include <stdio.h>
+
+#if defined(__riscv)
+#  include <riscv_vector.h>
+#  define CV_RVV 1
+#endif
+
+#if defined CV_RVV
+int test()
+{
+    const float src[] = { 0.0f, 0.0f, 0.0f, 0.0f };
+    vfloat32m1_t val = vle32_v_f32m1((const float*)(src));
+    return (int)vfmv_f_s_f32m1_f32(val);
+}
+#else
+#error "RISC-V vector extension(RVV) is not supported"
+#endif
+
+int main()
+{
+  printf("%d\n", test());
+  return 0;
+}

modules/core/include/opencv2/core/cv_cpu_dispatch.h

@@ -168,6 +168,10 @@
 #  include <wasm_simd128.h>
 #endif
 
+#if defined CV_CPU_COMPILE_RVV
+#  define CV_RVV 1
+#endif
+
 #endif // CV_ENABLE_INTRINSICS && !CV_DISABLE_OPTIMIZATION && !__CUDACC__
 
 #if defined CV_CPU_COMPILE_AVX && !defined CV_CPU_BASELINE_COMPILE_AVX
@@ -343,3 +347,7 @@ struct VZeroUpperGuard {
 #ifndef CV_WASM_SIMD
 #  define CV_WASM_SIMD 0
 #endif
+
+#ifndef CV_RVV
+#  define CV_RVV 0
+#endif

modules/core/include/opencv2/core/cv_cpu_helper.h

@@ -483,5 +483,26 @@
 #endif
 #define __CV_CPU_DISPATCH_CHAIN_VSX3(fn, args, mode, ...)  CV_CPU_CALL_VSX3(fn, args); __CV_EXPAND(__CV_CPU_DISPATCH_CHAIN_ ## mode(fn, args, __VA_ARGS__))
 
+#if !defined CV_DISABLE_OPTIMIZATION && defined CV_ENABLE_INTRINSICS && defined CV_CPU_COMPILE_RVV
+#  define CV_TRY_RVV 1
+#  define CV_CPU_FORCE_RVV 1
+#  define CV_CPU_HAS_SUPPORT_RVV 1
+#  define CV_CPU_CALL_RVV(fn, args) return (cpu_baseline::fn args)
+#  define CV_CPU_CALL_RVV_(fn, args) return (opt_RVV::fn args)
+#elif !defined CV_DISABLE_OPTIMIZATION && defined CV_ENABLE_INTRINSICS && defined CV_CPU_DISPATCH_COMPILE_RVV
+#  define CV_TRY_RVV 1
+#  define CV_CPU_FORCE_RVV 0
+#  define CV_CPU_HAS_SUPPORT_RVV (cv::checkHardwareSupport(CV_CPU_RVV))
+#  define CV_CPU_CALL_RVV(fn, args) if (CV_CPU_HAS_SUPPORT_RVV) return (opt_RVV::fn args)
+#  define CV_CPU_CALL_RVV_(fn, args) if (CV_CPU_HAS_SUPPORT_RVV) return (opt_RVV::fn args)
+#else
+#  define CV_TRY_RVV 0
+#  define CV_CPU_FORCE_RVV 0
+#  define CV_CPU_HAS_SUPPORT_RVV 0
+#  define CV_CPU_CALL_RVV(fn, args)
+#  define CV_CPU_CALL_RVV_(fn, args)
+#endif
+#define __CV_CPU_DISPATCH_CHAIN_RVV(fn, args, mode, ...)  CV_CPU_CALL_RVV(fn, args); __CV_EXPAND(__CV_CPU_DISPATCH_CHAIN_ ## mode(fn, args, __VA_ARGS__))
+
 #define CV_CPU_CALL_BASELINE(fn, args) return (cpu_baseline::fn args)
 #define __CV_CPU_DISPATCH_CHAIN_BASELINE(fn, args, mode, ...)  CV_CPU_CALL_BASELINE(fn, args) /* last in sequence */

modules/core/include/opencv2/core/cvdef.h

@@ -260,6 +260,8 @@ namespace cv {
 #define CV_CPU_VSX              200
 #define CV_CPU_VSX3             201
 
+#define CV_CPU_RVV              210
+
 // CPU features groups
 #define CV_CPU_AVX512_SKX       256
 #define CV_CPU_AVX512_COMMON    257
@@ -312,6 +314,8 @@ enum CpuFeatures {
     CPU_VSX             = 200,
     CPU_VSX3            = 201,
 
+    CPU_RVV             = 210,
+
     CPU_AVX512_SKX      = 256, //!< Skylake-X with AVX-512F/CD/BW/DQ/VL
     CPU_AVX512_COMMON   = 257, //!< Common instructions AVX-512F/CD for all CPUs that support AVX-512
     CPU_AVX512_KNL      = 258, //!< Knights Landing with AVX-512F/CD/ER/PF

modules/core/include/opencv2/core/hal/intrin.hpp

@@ -199,6 +199,7 @@ using namespace CV_CPU_OPTIMIZATION_HAL_NAMESPACE;
 #   undef CV_VSX
 #   undef CV_FP16
 #   undef CV_MSA
+#   undef CV_RVV
 #endif
 
 #if (CV_SSE2 || CV_NEON || CV_VSX || CV_MSA || CV_WASM_SIMD) && !defined(CV_FORCE_SIMD128_CPP)
@@ -226,6 +227,9 @@ using namespace CV_CPU_OPTIMIZATION_HAL_NAMESPACE;
 #elif CV_WASM_SIMD && !defined(CV_FORCE_SIMD128_CPP)
 #include "opencv2/core/hal/intrin_wasm.hpp"
 
+#elif CV_RVV && !defined(CV_FORCE_SIMD128_CPP)
+#include "opencv2/core/hal/intrin_rvv.hpp"
+
 #else
 
 #include "opencv2/core/hal/intrin_cpp.hpp"