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ALU.vhd

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+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   ALU.vhd
+-- Deskripsi        :   blok ALU
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+ENTITY ALU IS
+PORT (
+	OPRND_1 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 1 
+	OPRND_2 : IN std_logic_vector (31 DOWNTO 0); -- Data Input 2
+	OP_SEL : IN std_logic; -- Operation Select
+	RESULT : OUT std_logic_vector (31 DOWNTO 0) -- Data Output
+);
+END ALU;
+
+ARCHITECTURE BEHAVIOUR of ALU IS
+COMPONENT CLA_32 IS
+PORT (
+		OPRND_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Operand 1
+		OPRND_2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- Operand 2
+		C_IN : IN STD_LOGIC; -- Carry In
+		RESULT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); -- Result
+		C_OUT : OUT STD_LOGIC -- Overflow
+);
+END COMPONENT;
+
+BEGIN
+
+ALU_BLOCK: CLA_32
+				PORT MAP(OPRND_1 => OPRND_1,
+							OPRND_2 => OPRND_2,
+							C_IN	  => OP_SEL,
+							RESULT  => RESULT,
+							C_OUT	  => OPEN);
+
+END BEHAVIOUR;

BR_INTERRUPT.vhd

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+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   BR_INTERRUPT.vhd
+-- Deskripsi        :   Blok kombinasional untuk selektor mux2to1 apabila branching
+
+LIBRARY ieee; 
+USE ieee.std_logic_1164.all; 
+USE ieee.numeric_std.all;
+
+ENTITY BR_INTERRUPT IS
+PORT(	sig_branch: IN STD_LOGIC;
+		sig_bne:		IN STD_LOGIC;
+		comp:			IN STD_LOGIC;
+		pc_sel:		OUT STD_LOGIC
+	);
+END BR_INTERRUPT;
+
+ARCHITECTURE BEHAVIOUR of BR_INTERRUPT IS
+BEGIN
+
+--Blok menentukan apakah PC dipilih target address atau hasil increment + 4
+pc_sel <= (sig_bne AND NOT(COMP)) OR (sig_branch AND COMP);
+
+END BEHAVIOUR;

CU.vhd

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+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   CU.vhd
+-- Deskripsi        :   Implementasi blok Control Unit
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+ENTITY cu IS
+PORT (
+			--INPUT
+			OP_In : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+			FUNCT_In : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+			--OUTPUT
+			Sig_Jmp : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+			Sig_Bne : OUT STD_LOGIC;
+			Sig_Branch : OUT STD_LOGIC;
+			Sig_MemtoReg : OUT STD_LOGIC;
+			Sig_MemRead : OUT STD_LOGIC;
+			Sig_MemWrite : OUT STD_LOGIC;
+			Sig_RegDest : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+			Sig_RegWrite : OUT STD_LOGIC;
+			Sig_ALUSrc : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+			Sig_ALUCtrl : OUT STD_LOGIC
+);
+END cu;
+
+ARCHITECTURE BEHAVIOURAL of cu IS
+SIGNAL JUMP: STD_LOGIC_VECTOR (1 DOWNTO 0);
+SIGNAL BNE:  STD_LOGIC;
+SIGNAL BRANCH: STD_LOGIC;
+SIGNAL MEMTOREG: STD_LOGIC;
+SIGNAL MEMREAD: STD_LOGIC;
+SIGNAL MEMWRITE: STD_LOGIC;
+SIGNAL REGDEST: STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL REGWRITE: STD_LOGIC;
+SIGNAL ALUSRC: STD_LOGIC_VECTOR (1 DOWNTO 0);
+SIGNAL ALUCTRL: STD_LOGIC;
+
+BEGIN
+--Kombinasional Output
+Sig_Jmp			<= 	JUMP;
+Sig_Bne			<= 	BNE;
+Sig_Branch		<= 	BRANCH;
+Sig_MemtoReg	<=		MEMTOREG;
+Sig_MemRead		<=		MEMREAD;
+Sig_MemWrite	<=		MEMWRITE;
+Sig_RegDest		<=		REGDEST;
+Sig_RegWrite	<=		REGWRITE;
+Sig_ALUSrc		<=		ALUSRC;
+Sig_ALUCtrl		<=		ALUCTRL;
+
+--Generate Sinyal Kontrol
+CONTROL:
+	PROCESS(OP_In, FUNCT_In)
+	BEGIN
+		IF ((OP_In = "000000") AND (FUNCT_In = "100000")) THEN --add
+			JUMP <= "00";
+			BNE  <= '0';
+			BRANCH <= '0';
+			MEMTOREG <= '0';
+			MEMREAD <= '0';
+			MEMWRITE <= '0';
+			REGDEST <= "01";
+			REGWRITE <= '1';
+			ALUSRC <= "00";
+			ALUCTRL <= '0';
+		ELSIF ((OP_In = "000000") AND (FUNCT_In = "100010")) THEN --sub
+			JUMP <= "00";
+			BNE  <= '0';
+			BRANCH <= '0';
+			MEMTOREG <= '0';
+			MEMREAD <= '0';
+			MEMWRITE <= '0';
+			REGDEST <= "01";
+			REGWRITE <= '1';
+			ALUSRC <= "00";
+			ALUCTRL <= '1';
+		ELSIF ((OP_In = "000100")) THEN	--beq
+			JUMP <= "00";
+			BNE  <= '0';
+			BRANCH <= '1';
+			MEMTOREG <= '0';
+			MEMREAD <= '0';
+			MEMWRITE <= '0';
+			REGDEST <= "--";
+			REGWRITE <= '0';
+			ALUSRC <= "--";
+			ALUCTRL <= '-';
+		ELSIF ((OP_In = "000101")) THEN --bne
+			JUMP <= "00";
+			BNE  <= '1';
+			BRANCH <= '0';
+			MEMTOREG <= '0';
+			MEMREAD <= '0';
+			MEMWRITE <= '0';
+			REGDEST <= "--";
+			REGWRITE <= '0';
+			ALUSRC <= "--";
+			ALUCTRL <= '-';
+		ELSIF ((OP_In = "001000")) THEN --addi
+			JUMP <= "00";
+			BNE  <= '0';
+			BRANCH <= '0';
+			MEMTOREG <= '0';
+			MEMREAD <= '0';
+			MEMWRITE <= '0';
+			REGDEST <= "00";
+			REGWRITE <= '1';
+			ALUSRC <= "01";
+			ALUCTRL <= '0';
+		ELSIF ((OP_In = "100011")) THEN --lw
+			JUMP <= "00";
+			BNE  <= '0';
+			BRANCH <= '0';
+			MEMTOREG <= '1';
+			MEMREAD <= '1';
+			MEMWRITE <= '0';
+			REGDEST <= "00";
+			REGWRITE <= '1';
+			ALUSRC <= "01";
+			ALUCTRL <= '0';
+		ELSIF ((OP_In = "101011")) THEN --sw
+			JUMP <= "00";
+			BNE  <= '0';
+			BRANCH <= '0';
+			MEMTOREG <= '0';
+			MEMREAD <= '0';
+			MEMWRITE <= '1';
+			REGDEST <= "00";
+			REGWRITE <= '0';
+			ALUSRC <= "01";
+			ALUCTRL <= '0';
+		ELSIF ((OP_In = "000010")) THEN --jmp
+			JUMP <= "01";
+			BNE  <= '0';
+			BRANCH <= '0';
+			MEMTOREG <= '0';
+			MEMREAD <= '0';
+			MEMWRITE <= '0';
+			REGDEST <= "--";
+			REGWRITE <= '0';
+			ALUSRC <= "--";
+			ALUCTRL <= '-';
+		ELSIF ((OP_In = "000000")) THEN --nop
+			JUMP <= "00";
+			BNE  <= '0';
+			BRANCH <= '0';
+			MEMTOREG <= '0';
+			MEMREAD <= '0';
+			MEMWRITE <= '0';
+			REGDEST <= "00";
+			REGWRITE <= '0';
+			ALUSRC <= "00";
+			ALUCTRL <= '0';
+		ELSE							--SUPAYA TIDAK ADA LATCH
+			JUMP <= "00";
+			BNE  <= '0';
+			BRANCH <= '0';
+			MEMTOREG <= '0';
+			MEMREAD <= '0';
+			MEMWRITE <= '0';
+			REGDEST <= "00";
+			REGWRITE <= '0';
+			ALUSRC <= "00";
+			ALUCTRL <= '0';
+		END IF;
+	END PROCESS CONTROL;
+
+END BEHAVIOURAL;

Instruction_Memory.vhd

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+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   Instruction_Memory.vhd
+-- Deskripsi        :   Implementasi blok Instruction_Memory
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+
+entity Instruction_Memory is
+    Port ( addr  : in	STD_LOGIC_VECTOR (31 downto 0);
+			  clock : in	STD_LOGIC;
+			  reset : in	STD_LOGIC;
+           instr : out  STD_LOGIC_VECTOR (31 downto 0));
+end Instruction_Memory;
+
+architecture Behavioral of Instruction_Memory is
+type mem is array(0 to 255) of std_logic_vector(31 downto 0);
+signal memory : mem := (
+		x"20100013",x"1000fffb",x"ac040000",x"1000ffff",
+		x"20110015",x"00000013",x"00000000",x"00000000",
+		x"16530001",x"00000011",x"00000000",x"00000003",
+		x"00000000",x"00000072",x"00000098",x"00000020",
+		x"02119822",x"00000000",x"00000000",x"00000004",
+		x"22730000",x"00000000",x"00000000",x"00000000",
+		x"22140004",x"00000000",x"00000000",x"00000000",
+		x"ae910000",x"00000000",x"00000000",x"00000000",
+		x"8e950000",x"00000000",x"00000000",x"00000000",
+		x"02a0a820",x"00000000",x"00000000",x"00000000",
+		x"08000000",x"00000000",x"00000000",x"00000000",
+		x"00000000",x"00000000",x"00000000",x"00000000",
+		others => x"00000000"
+		);
+
+signal wire_in: STD_LOGIC_VECTOR(31 DOWNTO 0);
+--signal instr_read: STD_LOGIC_VECTOR (31 downto 0);
+
+begin
+
+--instr_read <= memory(to_integer(unsigned(ADDR)));
+wire_in <= addr;
+
+	process(clock, reset, addr, memory)
+	begin
+		if (reset = '1') then
+			instr <= (others => '0');
+		elsif (rising_edge(clock)) then
+			instr <= memory(to_integer(unsigned(wire_in)));
+		end if;
+	end process;
+
+end Behavioral;

PC.vhd

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+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   PC.vhd
+-- Deskripsi        :   Implementasi blok Program Counter
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+
+entity PC is
+    Port ( clock:		in  STD_LOGIC;
+           PC_in:		in  STD_LOGIC_VECTOR(31 DOWNTO 0);
+           PC_out:	out STD_LOGIC_VECTOR (31 downto 0));
+end PC;
+
+architecture Behavioral of PC is
+SIGNAL wire_in:  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL wire_out: STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+
+BEGIN
+
+--Kombinasional
+	wire_in  <= PC_in;
+	PC_out	<= wire_out;
+
+	process(clock)
+	begin
+		if(rising_edge(clock)) then
+			wire_out <= wire_in;
+		end if;
+	end process;
+
+end Behavioral;

bus_merger.vhd

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+-- Praktikum EL3111 Arsitektur Sistem Komputer
+-- Modul            :   5
+-- Percobaan        :   1 dan 2
+-- Tanggal          :   25 November 2021
+-- Rombongan        :   C (tuker dari A)
+-- Nama (NIM)       :   Christian Reivan (13219005)
+-- Nama File        :   bus_merger.vhd
+-- Deskripsi        :   Implementasi blok bus_merger
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+ENTITY bus_merger IS
+PORT (
+			DATA_IN1 : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+			DATA_IN2 : IN STD_LOGIC_VECTOR (27 DOWNTO 0);
+			DATA_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+);
+END bus_merger;
+
+ARCHITECTURE BEHAVIOURAL of bus_merger IS
+BEGIN
+
+DATA_OUT <= DATA_IN1 & DATA_IN2;
+
+END BEHAVIOURAL;