Switch to EmbeddedRiscvJtag and openocd-risv

.github/docker/Dockerfile

@@ -18,7 +18,7 @@ RUN apt-get update \
   && apt-get clean \
   && rm -rf /var/lib/apt/lists/*
 
-FROM builder AS build-openocd-vexriscv
+FROM builder AS build-openocd-riscv
 
 ARG DEPS_OPENOCD_VEXRISCV="autoconf automake libtool pkg-config libusb-1.0-0-dev libftdi-dev libhidapi-dev libusb-dev libyaml-dev"
 
@@ -78,5 +78,5 @@ RUN apt-get update \
   && rm -rf /var/lib/apt/lists/*
 
 COPY --from=build-verilator /opt /opt
-COPY --from=build-openocd-vexriscv /opt /opt
+COPY --from=build-openocd-riscv /opt /opt
 COPY --from=build-ghc /root/.ghcup /root/.ghcup

.github/docker/build-and-publish-docker-image.sh

@@ -17,13 +17,15 @@ elif [[ "$1" != "" ]]; then
 fi
 
 UBUNTU_VERSION=jammy-20240125
-GHC_VERSIONS=( "9.6.6"  "9.4.8"  "9.2.8"   "9.0.2")
-CABAL_VERSION="3.10.2.0"
+GHC_VERSIONS=( "9.10.1"  "9.8.4"  "9.6.6"  "9.4.8"  "9.2.8"   "9.0.2")
+CABAL_VERSION="3.12.1.0"
 
 for i in "${!GHC_VERSIONS[@]}"
 do
   GHC_VERSION="${GHC_VERSIONS[i]}"
 
+  # If you get an error like "unrecognized argument buildx", consider installing
+  # the buildx plugin for Docker. E.g., for Ubuntu: `apt install docker-buildx`.
   docker buildx build \
     --build-arg UBUNTU_VERSION=${UBUNTU_VERSION} \
     --build-arg cabal_version=${CABAL_VERSION} \

.github/workflows/ci.yml

@@ -117,7 +117,7 @@ jobs:
           - "9.6.6"
 
     container:
-      image: ghcr.io/clash-lang/clash-vexriscv-ci:${{ matrix.ghc }}-20240823
+      image: ghcr.io/clash-lang/clash-vexriscv-ci:${{ matrix.ghc }}-20241214
 
     steps:
       - name: Checkout
@@ -165,7 +165,7 @@ jobs:
 
       - name: OpenOCD bin symlink
         run: |
-          ln -s /opt/bin/openocd /opt/bin/openocd-vexriscv
+          ln -s /opt/bin/openocd /opt/bin/openocd-riscv
 
       - name: Run `clash-vexriscv` unittests
         run: |

.gitignore

@@ -71,3 +71,9 @@ simulation_dump.vcd
 
 # Clash output
 verilog
+
+# Metals vscode extension
+.metals
+
+# Scala
+.scala-build

clash-vexriscv-sim/app/VexRiscvChainSimulation.hs

@@ -76,7 +76,7 @@ getRunOpts = RunOpts
     )
 
 jtagDaisyChain :: JtagIn -> JtagOut -> JtagIn
-jtagDaisyChain (JtagIn tc ms _) (JtagOut to _) = JtagIn tc ms to
+jtagDaisyChain (JtagIn tc ms _) (JtagOut to _ _) = JtagIn tc ms to
 
 type CpuSignals =
   ( CpuOut
@@ -120,7 +120,7 @@ main = do
 
     _jtagReset = L.foldl (liftA2 go1) (pure False) [jtagOutA, jtagOutB]
      where
-      go1 acc (JtagOut _ tr) = acc || bitToBool tr
+      go1 acc (JtagOut _ _ tr) = acc || bitToBool tr
 
     cpuOut = bundle (cpuOutA, cpuOutB)
 

clash-vexriscv-sim/data/vexriscv_chain_sim.cfg

@@ -1,6 +1,6 @@
 # Execute using:
 #
-#   openocd-vexriscv -f vexriscv_sim_chain.cfg
+#   openocd-riscv -f vexriscv_sim_chain.cfg
 #
 
 # SPDX-FileCopyrightText: 2024 Google LLC
@@ -9,32 +9,27 @@
 
 # See vexriscv_sim.cfg for more information on each step taken.
 
-adapter driver jtag_tcp
-adapter speed 64000
+adapter driver remote_bitbang
 transport select jtag
-
+remote_bitbang host 127.0.0.1
+remote_bitbang port 7894
 
 set  _ENDIAN little
 set _TAP_TYPE 1234
 
 if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
-   set _CPUTAPID 0x10001fff
+   set _CPUTAPID 0x10002FFF
 }
 
-set _CHIPNAME vexrisc_ocd
-
-jtag newtap $_CHIPNAME chain0 -expected-id $_CPUTAPID -irlen 4 -ircapture 0x1 -irmask 0x0F
-jtag newtap $_CHIPNAME chain1 -expected-id $_CPUTAPID -irlen 4 -ircapture 0x1 -irmask 0x03
+set _CHIPNAME riscv
 
-target create $_CHIPNAME.cpu0 vexriscv -endian $_ENDIAN -chain-position $_CHIPNAME.chain1
-vexriscv readWaitCycles 10
-vexriscv cpuConfigFile clash-vexriscv/example-cpu/ExampleCpu.yaml
+jtag newtap $_CHIPNAME chain0 -expected-id $_CPUTAPID -irlen 5
+jtag newtap $_CHIPNAME chain1 -expected-id $_CPUTAPID -irlen 5
 
-target create $_CHIPNAME.cpu1 vexriscv -endian $_ENDIAN -chain-position $_CHIPNAME.chain0
-vexriscv readWaitCycles 10
-vexriscv cpuConfigFile clash-vexriscv/example-cpu/ExampleCpu.yaml
+target create $_CHIPNAME.cpu0 riscv -endian $_ENDIAN -chain-position $_CHIPNAME.chain1
+target create $_CHIPNAME.cpu1 riscv -endian $_ENDIAN -chain-position $_CHIPNAME.chain0
 
 poll_period 50
 

clash-vexriscv-sim/data/vexriscv_sim.cfg

@@ -1,16 +1,15 @@
 # Execute using:
 #
-#   openocd-vexriscv -f vexriscv_sim.cfg
+#   openocd-riscv -f vexriscv_sim.cfg
 #
 
 # SPDX-FileCopyrightText: 2024 Google LLC
 #
 # SPDX-License-Identifier: CC0-1.0
-
-adapter driver jtag_tcp
-adapter speed 64000
+adapter driver remote_bitbang
 transport select jtag
-
+remote_bitbang host 127.0.0.1
+remote_bitbang port 7894
 
 set  _ENDIAN little
 set _TAP_TYPE 1234
@@ -19,36 +18,20 @@ if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
   # set useful default
-   set _CPUTAPID 0x10001fff
+   set _CPUTAPID 0x10002FFF
 }
 
-set _CHIPNAME vexrisc_ocd
+set _CHIPNAME riscv
 
 # The JTAG TAP itself is given the name "bridge", because it refers to the
 # JtagBridge that's part of the VexRiscv/SpinalHDL debug infrastructure.
 # In the example design, there is the JtagBridge controls a single CPU, but
 # the capability is there for 1 JTAG TAP + JtagBridge to control multiple
 # VexRiscv CPUs.
-jtag newtap $_CHIPNAME bridge -expected-id $_CPUTAPID -irlen 4 -ircapture 0x1 -irmask 0xF
+jtag newtap $_CHIPNAME bridge -expected-id $_CPUTAPID -irlen 5
 
 # There is 1 CPU controlled by the "bridge" JTAG TAP, "cpu0"
-target create $_CHIPNAME.cpu0 vexriscv -endian $_ENDIAN -chain-position $_CHIPNAME.bridge
-
-# The JtagBridge/SystemDebugger receives commands in a serialized way. It gets synchronized into
-# a parallel bus, and a response is received. Along the way, there may be various clock domain
-# crossings or pipeline delays.
-# readWaitCycles instructs OpenOCD to insert idle JTAG clock cycles before shifting out
-# the response.
-# There aren't many transactions where read-back throughput is important, so there's little
-# points in lowballing this number.
-vexriscv readWaitCycles 10
-
-# When the Verilog of a SpinalHDL design with one or more VexRiscv CPUs is created, the system
-# also creates a .yaml file with information that's sideband information that's important for
-# OpenOCD to control the CPU correctly.
-# A good example of this are the number of hardware breakpoints that are supported by the CPU.
-vexriscv cpuConfigFile clash-vexriscv/example-cpu/ExampleCpu.yaml
-
+target create $_CHIPNAME.cpu0 riscv -endian $_ENDIAN -chain-position $_CHIPNAME.bridge
 # The rate at which OpenOCD polls active JTAG TAPs to check if there has been a notable
 # event. (E.g. to check if the CPU has hit a breakpoint.)
 # For some reason, making this number really low has an impact on the CPU while semihosting is

clash-vexriscv-sim/src/Utils/Cpu.hs

@@ -65,7 +65,7 @@ cpu dumpVcd jtagIn0 bootIMem bootDMem =
 
     jtagReset =
       unsafeFromActiveHigh $ register False $
-        bitToBool . debugReset <$> jtagOut
+        bitToBool . ndmreset <$> jtagOut
 
     jtagIn1 = fromMaybe (pure JTag.defaultIn) jtagIn0
 

clash-vexriscv-sim/tests/Tests/Jtag.hs

@@ -105,7 +105,7 @@ test debug = do
       , cwd = Just projectRoot
     }
 
-    openOcdProc = (proc "openocd-vexriscv" ["-f", openocdCfgPath]){
+    openOcdProc = (proc "openocd-riscv" ["-f", openocdCfgPath]){
         std_err = CreatePipe
       , cwd = Just projectRoot
     }
@@ -117,18 +117,23 @@ test debug = do
 
   withCreateProcess vexRiscvProc $ \_ (fromJust -> vexRiscvStdOut) _ _ -> do
     hSetBuffering vexRiscvStdOut LineBuffering
+    putStrLn "Expecting \"[CPU] a\" on vexRiscvStdOut"
     expectLine debug vexRiscvStdOut "[CPU] a"
 
     -- CPU has started, so we can start OpenOCD
     withCreateProcess openOcdProc $ \_ _ (fromJust -> openOcdStdErr) _ -> do
       hSetBuffering openOcdStdErr LineBuffering
+      putStrLn "Waiting for \"Halting processor\" on openOcdStdErr"
       waitForLine debug openOcdStdErr "Halting processor"
 
       -- OpenOCD has started, so we can start GDB
       withCreateProcess gdbProc $ \_ _ _ gdbProcHandle -> do
+        putStrLn "Expecting \"[CPU] a\" on vexRiscvStdOut"
         expectLine debug vexRiscvStdOut "[CPU] a"
+        putStrLn "Expecting \"[CPU] b\" on vexRiscvStdOut"
         expectLine debug vexRiscvStdOut "[CPU] b"
 
+        putStrLn "Waiting for gdb to exit"
         gdbExitCode <- waitForProcess gdbProcHandle
         ExitSuccess @?= gdbExitCode
 

clash-vexriscv-sim/tests/Tests/JtagChain.hs

@@ -62,19 +62,19 @@ test debug = do
       , cwd = Just projectRoot
       }
 
-    openOcdProc = (proc "openocd-vexriscv" ["-f", openocdCfgPath])
+    openOcdProc = (proc "openocd-riscv" ["-f", openocdCfgPath])
       { std_err = CreatePipe
       , cwd = Just projectRoot
       }
 
     gdbProcA = (proc gdb ["--command", gdbCmdPathA])
-      { std_out = CreatePipe
-      , cwd = Just projectRoot
+      { cwd = Just projectRoot
+      , std_out = CreatePipe
       }
 
     gdbProcB = (proc gdb ["--command", gdbCmdPathB])
-      { std_out = CreatePipe
-      , cwd = Just projectRoot
+      { cwd = Just projectRoot
+      , std_out = CreatePipe
       }
 
   withCreateProcess vexRiscvProc $ \_ _ _ _ -> do