Support implementation of architecture_spec config.

include/ArchitectureSpec/architecture.yaml

@@ -1,19 +1,19 @@
 architecture:
   name: "NeuraCGRA"
   version: "1.0"
-  width: 4
-  height: 4
+  width: 8
+  height: 8
 
 tile_defaults:
-  num_registers: 64
+  num_registers: 128
   default_ports: ["N", "S", "W", "E"]
-  operations: ["add", "mul", "sub"]  # default ALU instructions
+  operations: ["add", "mul", "sub", "div", "rem", "fadd", "fmul", "fsub", "fdiv", "or", "not", "icmp", "fcmp", "sel", "cast", "sext", "zext", "shl", "vfmul", "fadd_fadd", "fmul_fadd", "data_mov", "ctrl_mov", "reserve", "grant_predicate", "grant_once", "grant_always", "loop_control", "phi", "constant"]  # comprehensive operation set
 
 link_defaults:
   latency: 1
   bandwidth: 32
 
-connectivity: "mesh"
+base_topology: "mesh"
 
 link_overrides:
   - id: 1
@@ -30,6 +30,12 @@ link_overrides:
     dst_tile_id: 8
     existence: true
 
+  - latency: 3
+    bandwidth: 32
+    src_tile_id: 0
+    dst_tile_id: 1
+    existence: true
+
 tile_overrides:
   - id: 0
     x: 0
@@ -62,7 +68,7 @@ tile_overrides:
     ports: ["E", "W"]
 
 extensions:
-  crossbar: false
+  placeholder: false
 
 simulator:
   execution_model: "serial"

include/NeuraDialect/Architecture/Architecture.h

@@ -1,6 +1,7 @@
 #ifndef NEURA_ARCHITECTURE_H
 #define NEURA_ARCHITECTURE_H
 
+#include <algorithm>
 #include <cassert>
 #include <map>
 #include <memory>
@@ -9,6 +10,8 @@
 #include <unordered_map>
 #include <vector>
 
+#include "NeuraDialect/Architecture/ArchitectureSpec.h"
+
 namespace mlir {
 namespace neura {
 
@@ -30,7 +33,32 @@ enum class FunctionUnitKind {
 };
 
 // Enum for supported operation types.
-enum OperationKind { IAdd = 0, IMul = 1, FAdd = 2, FMul = 3 };
+enum OperationKind { 
+  // Integer arithmetic operations.
+  IAdd = 0, IMul = 1, ISub = 2, IDiv = 3, IRem = 4,
+  // Floating-point arithmetic operations.
+  FAdd = 5, FMul = 6, FSub = 7, FDiv = 8,
+  // Memory operations.
+  ILoad = 9, IStore = 10, ILoadIndexed = 11, IStoreIndexed = 12, IAlloca = 13,
+  // Logical operations.
+  IOr = 14, INot = 15, ICmp = 16, FCmp = 17, ISel = 18,
+  // Type conversion operations.
+  ICast = 19, ISExt = 20, IZExt = 21, IShl = 22,
+  // Vector operations.
+  VFMul = 23,
+  // Fused operations.
+  FAddFAdd = 24, FMulFAdd = 25,
+  // Control flow operations.
+  IReturn = 26, IPhi = 27,
+  // Data movement operations.
+  IDataMov = 28, ICtrlMov = 29,
+  // Predicate operations.
+  IReserve = 30, IGrantPredicate = 31, IGrantOnce = 32, IGrantAlways = 33,
+  // Loop control operations.
+  ILoopControl = 34,
+  // Constant operations.
+  IConstant = 35
+};
 
 //===----------------------------------------------------------------------===//
 // BasicResource: abstract base class for Tile, Link, etc.
@@ -94,24 +122,6 @@ class FunctionUnit : public BasicResource {
   Tile *tile;
 };
 
-class FixedPointAdder : public FunctionUnit {
-public:
-  FixedPointAdder(int id) : FunctionUnit(id) {
-    supported_operations.insert(OperationKind::IAdd);
-  }
-  std::string getType() const override { return "fixed_point_adder"; }
-  ResourceKind getKind() const override { return ResourceKind::FunctionUnit; }
-};
-
-class FixedPointMultiplier : public FunctionUnit {
-public:
-  FixedPointMultiplier(int id) : FunctionUnit(id) {
-    supported_operations.insert(OperationKind::IMul);
-  }
-  std::string getType() const override { return "fixed_point_multiplier"; }
-  ResourceKind getKind() const override { return ResourceKind::FunctionUnit; }
-};
-
 class CustomizableFunctionUnit : public FunctionUnit {
 public:
   CustomizableFunctionUnit(int id) : FunctionUnit(id) {}
@@ -143,6 +153,7 @@ class Tile : public BasicResource {
   int getY() const;
 
   void linkDstTile(Link *link, Tile *tile);
+  void unlinkDstTile(Link *link, Tile *tile);
   const std::set<Tile *> &getDstTiles() const;
   const std::set<Tile *> &getSrcTiles() const;
   const std::set<Link *> &getOutLinks() const;
@@ -155,16 +166,20 @@ class Tile : public BasicResource {
     functional_units.insert(functional_unit_storage.back().get());
   }
 
+  void clearFunctionUnits() {
+    functional_unit_storage.clear();
+    functional_units.clear();
+  }
+
   bool canSupportOperation(OperationKind operation) const {
     for (FunctionUnit *fu : functional_units) {
       if (fu->canSupportOperation(operation)) {
         return true;
       }
     }
-    // TODO: Check if the tile can support the operation based on its
-    // capabilities.
-    // @Jackcuii, https://github.com/coredac/dataflow/issues/82.
-    return true;
+    // Check if any function unit in this tile supports the operation.
+    // This is now properly implemented by checking all functional units.
+    return false;
   }
 
   void addRegisterFileCluster(RegisterFileCluster *register_file_cluster);
@@ -175,6 +190,17 @@ class Tile : public BasicResource {
 
   const std::vector<Register *> getRegisters() const;
 
+  // Port management.
+  const std::vector<std::string> &getPorts() const { return ports; }
+  void setPorts(const std::vector<std::string> &new_ports) { ports = new_ports; }
+  bool hasPort(const std::string &port) const {
+    return std::find(ports.begin(), ports.end(), port) != ports.end();
+  }
+
+  // Memory management.
+  int getMemoryCapacity() const { return memory_capacity; }
+  void setMemoryCapacity(int capacity) { memory_capacity = capacity; }
+
 private:
   int id;
   int x, y;
@@ -186,6 +212,10 @@ class Tile : public BasicResource {
       functional_unit_storage;               // Owns FUs.
   std::set<FunctionUnit *> functional_units; // Non-owning, for fast lookup.
   RegisterFileCluster *register_file_cluster = nullptr;
+
+  // Port and memory configuration.
+  std::vector<std::string> ports;
+  int memory_capacity = -1;  // -1 means not configured.
 };
 
 //===----------------------------------------------------------------------===//
@@ -210,10 +240,18 @@ class Link : public BasicResource {
 
   void connect(Tile *src, Tile *dst);
 
+  // Link properties.
+  int getLatency() const { return latency; }
+  int getBandwidth() const { return bandwidth; }
+  void setLatency(int l) { latency = l; }
+  void setBandwidth(int b) { bandwidth = b; }
+
 private:
   int id;
   Tile *src_tile;
   Tile *dst_tile;
+  int latency = 1;        // Latency in cycles.
+  int bandwidth = 32;     // Bandwidth in bits per cycle
 };
 
 //===----------------------------------------------------------------------===//
@@ -318,11 +356,23 @@ struct PairHash {
   }
 };
 
+// Forward declaration
+struct TileDefaults;
+struct TileOverride;
+struct LinkDefaults;
+struct LinkOverride;
+
 // Describes the CGRA architecture template.
-// TODO: Model architecture in detail (e.g., registers, ports).
+// Now supports comprehensive configuration via YAML including ports, memory, and function units.
 class Architecture {
 public:
-  Architecture(int width, int height);
+  // Single constructor - handles all cases internally.
+  Architecture(int width, int height, 
+               const TileDefaults& tile_defaults,
+               const std::vector<TileOverride>& tile_overrides,
+               const LinkDefaults& link_defaults,
+               const std::vector<LinkOverride>& link_overrides,
+               BaseTopology base_topology = BaseTopology::MESH);
 
   Tile *getTile(int id);
   Tile *getTile(int x, int y);
@@ -331,14 +381,32 @@ class Architecture {
   int getHeight() const { return height; }
 
   Link *getLink(int id);
+  void removeLink(int link_id);
 
   int getNumTiles() const;
   std::vector<Tile *> getAllTiles() const;
   std::vector<Link *> getAllLinks() const;
 
 private:
-  // TODO: Model architecture in detail, e.g., ports, registers, crossbars, etc.
-  // https://github.com/coredac/dataflow/issues/52.
+  // Helper methods for constructor initialization.
+  void initializeTiles(int width, int height);
+  void configureDefaultTileSettings(const TileDefaults& tile_defaults);
+  void applyTileOverrides(const std::vector<TileOverride>& tile_overrides);
+  void createLinks(const LinkDefaults& link_defaults, BaseTopology base_topology);
+  void applyLinkOverrides(const std::vector<LinkOverride>& link_overrides);
+  void createRegisterFileCluster(Tile *tile, int num_registers, int &reg_id);
+  void recreateRegisterFileCluster(Tile *tile, int num_registers);
+  bool linkExists(Tile *src_tile, Tile *dst_tile);
+
+  // Helper methods for creating different topology links.
+  void createSingleLink(int &link_id, Tile *src_tile, Tile *dst_tile, const LinkDefaults& link_defaults);
+  void createLinkIfValid(int &link_id, Tile *src_tile, int dst_x, int dst_y, const LinkDefaults& link_defaults);
+  void createMeshLinks(int &link_id, const LinkDefaults& link_defaults);
+  void createKingMeshLinks(int &link_id, const LinkDefaults& link_defaults);
+  void createRingLinks(int &link_id, const LinkDefaults& link_defaults);
+
+  // Architecture components: tiles, links, and their mappings.
+  // Ports and memory are now modeled as part of Tile class.
   std::vector<std::unique_ptr<Tile>> tile_storage;
   std::vector<std::unique_ptr<Link>> link_storage;
   std::unordered_map<int, Tile *> id_to_tile;

include/NeuraDialect/Architecture/ArchitectureSpec.h

@@ -0,0 +1,65 @@
+#ifndef NEURA_ARCHITECTURE_SPEC_H
+#define NEURA_ARCHITECTURE_SPEC_H
+
+#include <string>
+#include <vector>
+
+namespace mlir {
+namespace neura {
+
+// Enumeration for base topology types
+enum class BaseTopology {
+  MESH,      // 4-connected mesh (N, S, W, E)
+  KING_MESH, // 8-connected mesh (N, S, W, E, NE, NW, SE, SW)
+  RING       // Ring topology (only outer boundary connections)
+};
+
+// Structure to hold tile default configuration
+struct TileDefaults {
+  int num_registers = 64;  // default value
+  std::vector<std::string> default_ports = {"N", "S", "W", "E"};  // default ports
+  std::vector<std::string> operations = {"add", "mul", "sub"};  // default operations
+};
+
+// Structure to hold memory configuration
+struct MemoryConfig {
+  int capacity = -1;  // Memory capacity in bytes
+};
+
+// Structure to hold tile override configuration
+struct TileOverride {
+  int id = -1;
+  int x = -1, y = -1;
+  std::vector<std::string> operations;
+  int num_registers = -1;
+  std::vector<std::string> ports;
+  MemoryConfig memory;
+};
+
+// Structure to hold link default configuration
+struct LinkDefaults {
+  int latency = 1;  // default latency
+  int bandwidth = 32;  // default bandwidth
+};
+
+// Structure to hold link override configuration
+struct LinkOverride {
+  int id = -1;
+  int latency = -1;
+  int bandwidth = -1;
+  int src_tile_id = -1;
+  int dst_tile_id = -1;
+  bool existence = true;
+};
+
+// Function to get the architecture specification file path
+// This is set by the command line tool when a YAML file is provided
+std::string getArchitectureSpecFile();
+
+// Function to get tile defaults configuration
+TileDefaults getTileDefaults();
+
+} // namespace neura
+} // namespace mlir
+
+#endif // NEURA_ARCHITECTURE_SPEC_H