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Pull Request Overview
This PR improves the code generation pass for CGRA (Coarse-Grained Reconfigurable Array) routing by fixing direction computation for cross-tile data movement and standardizing variable naming conventions.
- Fixes direction rewiring logic to correctly compute incoming directions when consumers are not located on link destination tiles
- Adds explicit direction inversion for incoming directions at destination tiles in register deposits
- Standardizes parameter naming from camelCase to snake_case throughout affected functions
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tancheng
reviewed
Nov 8, 2025
tancheng
approved these changes
Nov 8, 2025
tancheng
reviewed
Nov 8, 2025
- Updated AFTER_CANONICALIZE expectations to match new canonicalize-live-in behavior (3 args instead of 4) - Updated ASM expectations to match new code generation output (II=12, PE(0,0) format) - Fixed FileCheck pattern to handle empty line between II and PE declarations
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Summary
When data moves between PEs via links with register mapping, the generated
ASM instructions use incorrect direction operands. For example, PE(2,1) should
receive data in histogram from PE(2,2) via NORTH direction, but the original code generated
SOUTH instead.
Changes:
Fix
handleRegisterRewiring: AddinvertDirwhen computingincoming_dirfor
placeDstDeposit. The deposit instruction is placed on the destinationtile and needs to know from which direction data arrives.
Fix
handleDirectionRewiring: Calculate direction based on consumer's actualtile location instead of assuming it's always on the link destination tile.
When consumer is on a different tile, compute the direction from destination
tile to consumer tile.
Files Changed:
invertDirfor register deposit directionhandleDirectionRewiringto handle consumers ondifferent tiles
topoparameter tohandleDirectionRewiring