update codegen and codegen test for diagonal direction

lib/NeuraDialect/Transforms/GenerateCodePass.cpp

@@ -244,6 +244,10 @@ struct Topology {
     if (dc == -1 && dr == 0) return "WEST";
     if (dc == 0 && dr == 1) return "NORTH";
     if (dc == 0 && dr == -1) return "SOUTH";
+    if (dc == 1 && dr == 1) return "NORTHEAST";
+    if (dc == -1 && dr == 1) return "NORTHWEST";
+    if (dc == 1 && dr == -1) return "SOUTHEAST";
+    if (dc == -1 && dr == -1) return "SOUTHWEST";
     return "LOCAL";
   }
   StringRef dirFromLink(int link_id) const {
@@ -256,6 +260,10 @@ struct Topology {
     if (d == "WEST") return "EAST";
     if (d == "NORTH") return "SOUTH";
     if (d == "SOUTH") return "NORTH";
+    if (d == "NORTHEAST") return "SOUTHWEST";
+    if (d == "NORTHWEST") return "SOUTHEAST";
+    if (d == "SOUTHEAST") return "NORTHWEST";
+    if (d == "SOUTHWEST") return "NORTHEAST";
     return "LOCAL";
   }
   int srcTileOfLink(int link_id) const { return link_ends.lookup(link_id).first; }

test/arch_spec/architecture_king_mesh.yaml

@@ -0,0 +1,102 @@
+architecture:
+  name: "NeuraMultiCgra"
+  version: "1.0"
+
+multi_cgra_defaults:
+  base_topology: "mesh"
+  rows: 1
+  columns: 1
+
+per_cgra_defaults:
+  rows: 4
+  columns: 4
+  ctrl_mem_items: 20
+  base_topology: "king_mesh"
+
+tile_defaults:
+  num_registers: 32
+  fu_types: ["add", "mul", "div", "fadd", "fmul", "fdiv", "logic", "cmp", "sel", "type_conv", "vfmul", "fadd_fadd", "fmul_fadd", "grant", "loop_control", "phi", "constant", "return", "alloca", "shift"]
+
+link_defaults:
+  latency: 1
+  bandwidth: 32
+
+link_overrides:
+
+tile_overrides:
+  # Enable memory FU only on the 7 boundary tiles:
+  # left column (0,0)..(0,3) and top/bottom row continuation (1,0)..(3,0).
+  - cgra_x: 0
+    cgra_y: 0
+    tile_x: 0
+    tile_y: 0
+    fu_types: ["add", "mul", "div", "fadd", "fmul", "fdiv", "logic", "cmp", "sel", "type_conv", "vfmul", "fadd_fadd", "fmul_fadd", "grant", "loop_control", "phi", "constant", "return", "alloca", "shift", "mem", "mem_indexed"]
+    num_registers: 32
+    existence: true
+
+  - cgra_x: 0
+    cgra_y: 0
+    tile_x: 0
+    tile_y: 1
+    fu_types: ["add", "mul", "div", "fadd", "fmul", "fdiv", "logic", "cmp", "sel", "type_conv", "vfmul", "fadd_fadd", "fmul_fadd", "grant", "loop_control", "phi", "constant", "return", "alloca", "shift", "mem", "mem_indexed"]
+    num_registers: 32
+    existence: true
+
+  - cgra_x: 0
+    cgra_y: 0
+    tile_x: 0
+    tile_y: 2
+    fu_types: ["add", "mul", "div", "fadd", "fmul", "fdiv", "logic", "cmp", "sel", "type_conv", "vfmul", "fadd_fadd", "fmul_fadd", "grant", "loop_control", "phi", "constant", "return", "alloca", "shift", "mem", "mem_indexed"]
+    num_registers: 32
+    existence: true
+
+  - cgra_x: 0
+    cgra_y: 0
+    tile_x: 0
+    tile_y: 3
+    fu_types: ["add", "mul", "div", "fadd", "fmul", "fdiv", "logic", "cmp", "sel", "type_conv", "vfmul", "fadd_fadd", "fmul_fadd", "grant", "loop_control", "phi", "constant", "return", "alloca", "shift", "mem", "mem_indexed"]
+    num_registers: 32
+    existence: true
+
+  - cgra_x: 0
+    cgra_y: 0
+    tile_x: 1
+    tile_y: 0
+    fu_types: ["add", "mul", "div", "fadd", "fmul", "fdiv", "logic", "cmp", "sel", "type_conv", "vfmul", "fadd_fadd", "fmul_fadd", "grant", "loop_control", "phi", "constant", "return", "alloca", "shift", "mem", "mem_indexed"]
+    num_registers: 32
+    existence: true
+
+  - cgra_x: 0
+    cgra_y: 0
+    tile_x: 2
+    tile_y: 0
+    fu_types: ["add", "mul", "div", "fadd", "fmul", "fdiv", "logic", "cmp", "sel", "type_conv", "vfmul", "fadd_fadd", "fmul_fadd", "grant", "loop_control", "phi", "constant", "return", "alloca", "shift", "mem", "mem_indexed"]
+    num_registers: 32
+    existence: true
+
+  - cgra_x: 0
+    cgra_y: 0
+    tile_x: 3
+    tile_y: 0
+    fu_types: ["add", "mul", "div", "fadd", "fmul", "fdiv", "logic", "cmp", "sel", "type_conv", "vfmul", "fadd_fadd", "fmul_fadd", "grant", "loop_control", "phi", "constant", "return", "alloca", "shift", "mem", "mem_indexed"]
+    num_registers: 32
+    existence: true
+
+extensions:
+  crossbar: false
+
+simulator:
+  execution_model: "serial"
+
+  logging:
+    enabled: true
+    file: "output.log"
+
+  driver:
+    name: "Driver"
+    frequency: "1GHz"
+
+  device:
+    name: "Device"
+    frequency: "1GHz"
+    bind_to_architecture: true