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Merged
ShangkunLi merged 2 commits into from
Mar 18, 2026
Merged

llvm.mlir.addressof Conversion Pattern #289

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3f2fbbb
add llvm conversion pattern
ShangkunLi Mar 18, 2026
2a09c74
modify tests
ShangkunLi Mar 18, 2026
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24 changes: 24 additions & 0 deletions lib/Conversion/LlvmToNeura/LlvmToNeuraPass.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -661,6 +661,29 @@ struct LlvmConstantToNeuraConstant : public OpRewritePattern<LLVM::ConstantOp> {
}
};

struct LlvmAddressOfToNeuraConstant
: public OpRewritePattern<LLVM::AddressOfOp> {
using OpRewritePattern::OpRewritePattern;

LogicalResult matchAndRewrite(LLVM::AddressOfOp op,
PatternRewriter &rewriter) const override {
// Represents address-of as a Neura constant carrying the referenced
// global symbol.
Attribute global_symbol_attr = op->getAttr("global_name");
if (!global_symbol_attr) {
return op.emitOpError("expects global_name attribute");
}

OperationState state(op.getLoc(), neura::ConstantOp::getOperationName());
state.addAttribute("value", global_symbol_attr);
state.addTypes(op.getType());

Operation *new_op = rewriter.create(state);
rewriter.replaceOp(op, new_op->getResults());
return success();
}
};

struct LlvmAllocaToNeuraAlloca : public OpRewritePattern<LLVM::AllocaOp> {
using OpRewritePattern::OpRewritePattern;

Expand Down Expand Up @@ -880,6 +903,7 @@ struct LowerLlvmToNeuraPass
RewritePatternSet populateLlvmToNeuraPatterns(MLIRContext *context) {
RewritePatternSet patterns(context);
patterns.add<LlvmConstantToNeuraConstant>(&getContext());
patterns.add<LlvmAddressOfToNeuraConstant>(&getContext());
// Vector operations must be registered before scalar operations
// to ensure vector types are matched first.
patterns.add<LlvmVMulToNeuraVMul>(&getContext());
Expand Down
0 ...fine2neura/bert/bert_node0/bert_node0.cpp → ...fine2neura/bert/bert_node0/bert_node0.cpp
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0 ...ine2neura/bert/bert_node0/bert_node0.mlir → ...ine2neura/bert/bert_node0/bert_node0.mlir
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0 ...fine2neura/bert/bert_node1/bert_node1.cpp → ...fine2neura/bert/bert_node1/bert_node1.cpp
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0 ...ine2neura/bert/bert_node1/bert_node1.mlir → ...ine2neura/bert/bert_node1/bert_node1.mlir
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0 ...fine2neura/bert/bert_node2/bert_node2.cpp → ...fine2neura/bert/bert_node2/bert_node2.cpp
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0 ...ine2neura/bert/bert_node2/bert_node2.mlir → ...ine2neura/bert/bert_node2/bert_node2.mlir
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0 ...ne2neura/bert/bert_node28/bert_node28.cpp → ...ne2neura/bert/bert_node28/bert_node28.cpp
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0 ...e2neura/bert/bert_node28/bert_node28.mlir → ...e2neura/bert/bert_node28/bert_node28.mlir
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0 ...fine2neura/bert/bert_node3/bert_node3.cpp → ...fine2neura/bert/bert_node3/bert_node3.cpp
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0 ...ine2neura/bert/bert_node3/bert_node3.mlir → ...ine2neura/bert/bert_node3/bert_node3.mlir
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0 ...fine2neura/bert/bert_node8/bert_node8.cpp → ...fine2neura/bert/bert_node8/bert_node8.cpp
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0 ...ine2neura/bert/bert_node8/bert_node8.mlir → ...ine2neura/bert/bert_node8/bert_node8.mlir
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0 ...fine2neura/bert/bert_node9/bert_node9.cpp → ...fine2neura/bert/bert_node9/bert_node9.cpp
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0 ...ine2neura/bert/bert_node9/bert_node9.mlir → ...ine2neura/bert/bert_node9/bert_node9.mlir
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0 ...neToNeura/complex-affine-expressions.mlir → ...ine2neura/complex-affine-expressions.mlir
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0 ...onversion/AffineToNeura/deep-nesting.mlir → ...Conversion/affine2neura/deep-nesting.mlir
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0 ...on/AffineToNeura/imperfect-ops-after.mlir → ...ion/affine2neura/imperfect-ops-after.mlir
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0 ...AffineToNeura/loop-nest-optimization.mlir → .../affine2neura/loop-nest-optimization.mlir
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0 ...rsion/AffineToNeura/single-iteration.mlir → ...ersion/affine2neura/single-iteration.mlir
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0 .../AffineToNeura/unsupported-affine-if.mlir → ...n/affine2neura/unsupported-affine-if.mlir
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0 test/arith2neura/add.mlir → test/Conversion/arith2neura/add.mlir
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40 changes: 40 additions & 0 deletions test/Conversion/c2llvm2mlir/global_mem_address/kernel.c
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@@ -0,0 +1,40 @@
// GEMV + ReLU + GEMV kernel chain for codegen tests (int-only).
// All three kernels are implemented directly inside main().

#define M 4
#define K 4
#define N 4

static int run_gemv_relu_gemv(void) {
// Inputs / outputs: filled by simulation; only shape M, N, K matter here.
static int A[M * K];
static int x[K];
static int y[M];

// Kernel 1: GEMV
for (int i = 0; i < M; ++i) {
int acc = 0;
for (int j = 0; j < K; ++j) {
acc += A[i * K + j] * x[j];
}
y[i] = acc;
}

// Kernel 2: ReLU
for (int i = 0; i < M; ++i) {
if (y[i] < 0) {
y[i] = 0;
}
}

// Return a checksum-like value so outputs are consumed.
int checksum = 0;
for (int i = 0; i < N; ++i) {
checksum += y[i];
}
return checksum & 0xFF;
}

int kernel_gemv_relu_gemv(void) { return run_gemv_relu_gemv(); }

int main(void) { return run_gemv_relu_gemv(); }
78 changes: 78 additions & 0 deletions test/Conversion/c2llvm2mlir/global_mem_address/kernel.mlir
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// Compiles an attention-style GEMM+Softmax+GEMM kernel to LLVM IR, imports to MLIR,
// then lowers via Neura.
// RUN: clang -S -emit-llvm -O3 -fno-vectorize -fno-unroll-loops -std=c11 \
// RUN: -o %t-kernel-full.ll %S/kernel.c
// RUN: llvm-extract --rfunc=".*kernel.*" %t-kernel-full.ll -o %t-kernel-only.ll
// RUN: mlir-translate --import-llvm %t-kernel-only.ll -o %t-kernel.mlir
//
// RUN: mlir-neura-opt %t-kernel.mlir \
// RUN: --assign-accelerator \
// RUN: --lower-llvm-to-neura \
// RUN: --promote-input-arg-to-const \
// RUN: --fold-constant \
// RUN: --canonicalize-return \
// RUN: --canonicalize-live-in \
// RUN: --leverage-predicated-value \
// RUN: --transform-ctrl-to-data-flow \
// RUN: --fold-constant \
// RUN: -o %t-dataflow.mlir
// RUN: FileCheck %s --input-file=%t-dataflow.mlir --check-prefix=DATAFLOW

// DATAFLOW: llvm.mlir.global external hidden unnamed_addr @run_gemv_relu_gemv.y() {addr_space = 0 : i32, alignment = 16 : i64, dso_local} : !llvm.array<4 x i32>
// DATAFLOW-NEXT: func.func @kernel_gemv_relu_gemv() -> (i32 {llvm.range = #llvm.constant_range<i32, 0, 256>}) attributes {CConv = #llvm.cconv<ccc>, accelerator = "neura", dataflow_mode = "predicate", linkage = #llvm.linkage<external>, memory_effects = #llvm.memory_effects<other = readwrite, argMem = none, inaccessibleMem = none>, no_unwind, passthrough = ["nofree", "norecurse", "nosync", ["uwtable", "2"], ["min-legal-vector-width", "0"], ["no-trapping-math", "true"], ["stack-protector-buffer-size", "8"], ["target-cpu", "x86-64"]], target_cpu = "x86-64", target_features = #llvm.target_features<["+cmov", "+cx8", "+fxsr", "+mmx", "+sse", "+sse2", "+x87"]>, tune_cpu = "generic", unnamed_addr = 1 : i64, visibility_ = 0 : i64} {
// DATAFLOW-NEXT: %0 = "neura.constant"() <{value = @run_gemv_relu_gemv.y}> : () -> !neura.data<!llvm.ptr, i1>
// DATAFLOW-NEXT: %1 = "neura.constant"() <{value = 0 : i8}> : () -> !neura.data<i8, i1>
// DATAFLOW-NEXT: %2 = "neura.constant"() <{value = 16 : i64}> : () -> !neura.data<i64, i1>
// DATAFLOW-NEXT: %3 = "neura.grant_once"() <{constant_value = 0 : i64}> : () -> !neura.data<i64, i1>
// DATAFLOW-NEXT: %4 = "neura.grant_once"() <{constant_value = 0 : i32}> : () -> !neura.data<i32, i1>
// DATAFLOW-NEXT: "neura.memset"(%0, %1, %2) <{is_volatile = false}> : (!neura.data<!llvm.ptr, i1>, !neura.data<i8, i1>, !neura.data<i64, i1>) -> ()
// DATAFLOW-NEXT: %5 = neura.reserve : !neura.data<i32, i1>
// DATAFLOW-NEXT: %6 = neura.phi_start %4, %5 : !neura.data<i32, i1>, !neura.data<i32, i1> -> !neura.data<i32, i1>
// DATAFLOW-NEXT: %7 = neura.reserve : !neura.data<i64, i1>
// DATAFLOW-NEXT: %8 = neura.phi_start %3, %7 : !neura.data<i64, i1>, !neura.data<i64, i1> -> !neura.data<i64, i1>
// DATAFLOW-NEXT: %9 = neura.reserve : !neura.data<i64, i1>
// DATAFLOW-NEXT: %10 = neura.phi_start %3, %9 : !neura.data<i64, i1>, !neura.data<i64, i1> -> !neura.data<i64, i1>
// DATAFLOW-NEXT: %11 = "neura.constant"() <{value = 0 : i32}> : () -> !neura.data<index, i1>
// DATAFLOW-NEXT: %12 = "neura.gep"(%11, %10) <{operandSegmentSizes = array<i32: 0, 2>}> {lhs_value = @run_gemv_relu_gemv.y} : (!neura.data<index, i1>, !neura.data<i64, i1>) -> !neura.data<!llvm.ptr, i1>
// DATAFLOW-NEXT: %13 = "neura.load"(%12) : (!neura.data<!llvm.ptr, i1>) -> !neura.data<i32, i1>
// DATAFLOW-NEXT: %14 = "neura.icmp"(%13) <{cmpType = "slt"}> {rhs_value = 0 : i32} : (!neura.data<i32, i1>) -> !neura.data<i1, i1>
// DATAFLOW-NEXT: %15 = neura.grant_predicate %12, %14 : !neura.data<!llvm.ptr, i1>, !neura.data<i1, i1> -> !neura.data<!llvm.ptr, i1>
// DATAFLOW-NEXT: %16 = neura.grant_predicate %8, %14 : !neura.data<i64, i1>, !neura.data<i1, i1> -> !neura.data<i64, i1>
// DATAFLOW-NEXT: %17 = neura.grant_predicate %6, %14 : !neura.data<i32, i1>, !neura.data<i1, i1> -> !neura.data<i32, i1>
// DATAFLOW-NEXT: %18 = "neura.not"(%14) : (!neura.data<i1, i1>) -> !neura.data<i1, i1>
// DATAFLOW-NEXT: %19 = neura.grant_predicate %8, %18 : !neura.data<i64, i1>, !neura.data<i1, i1> -> !neura.data<i64, i1>
// DATAFLOW-NEXT: %20 = neura.grant_predicate %6, %18 : !neura.data<i32, i1>, !neura.data<i1, i1> -> !neura.data<i32, i1>
// DATAFLOW-NEXT: "neura.store"(%15) {lhs_value = 0 : i32} : (!neura.data<!llvm.ptr, i1>) -> ()
// DATAFLOW-NEXT: %21 = "neura.phi"(%20, %17) : (!neura.data<i32, i1>, !neura.data<i32, i1>) -> !neura.data<i32, i1>
// DATAFLOW-NEXT: %22 = "neura.phi"(%19, %16) : (!neura.data<i64, i1>, !neura.data<i64, i1>) -> !neura.data<i64, i1>
// DATAFLOW-NEXT: %23 = "neura.add"(%10) {rhs_value = 1 : i64} : (!neura.data<i64, i1>) -> !neura.data<i64, i1>
// DATAFLOW-NEXT: %24 = "neura.icmp"(%23) <{cmpType = "eq"}> {rhs_value = 4 : i64} : (!neura.data<i64, i1>) -> !neura.data<i1, i1>
// DATAFLOW-NEXT: %25 = "neura.not"(%24) : (!neura.data<i1, i1>) -> !neura.data<i1, i1>
// DATAFLOW-NEXT: %26 = neura.grant_predicate %23, %25 : !neura.data<i64, i1>, !neura.data<i1, i1> -> !neura.data<i64, i1>
// DATAFLOW-NEXT: neura.ctrl_mov %26 -> %9 : !neura.data<i64, i1> !neura.data<i64, i1>
// DATAFLOW-NEXT: %27 = neura.grant_predicate %22, %25 : !neura.data<i64, i1>, !neura.data<i1, i1> -> !neura.data<i64, i1>
// DATAFLOW-NEXT: neura.ctrl_mov %27 -> %7 : !neura.data<i64, i1> !neura.data<i64, i1>
// DATAFLOW-NEXT: %28 = neura.grant_predicate %21, %25 : !neura.data<i32, i1>, !neura.data<i1, i1> -> !neura.data<i32, i1>
// DATAFLOW-NEXT: neura.ctrl_mov %28 -> %5 : !neura.data<i32, i1> !neura.data<i32, i1>
// DATAFLOW-NEXT: %29 = neura.grant_predicate %22, %24 : !neura.data<i64, i1>, !neura.data<i1, i1> -> !neura.data<i64, i1>
// DATAFLOW-NEXT: %30 = neura.grant_predicate %21, %24 : !neura.data<i32, i1>, !neura.data<i1, i1> -> !neura.data<i32, i1>
// DATAFLOW-NEXT: %31 = neura.reserve : !neura.data<i32, i1>
// DATAFLOW-NEXT: %32 = neura.phi_start %30, %31 : !neura.data<i32, i1>, !neura.data<i32, i1> -> !neura.data<i32, i1>
// DATAFLOW-NEXT: %33 = neura.reserve : !neura.data<i64, i1>
// DATAFLOW-NEXT: %34 = neura.phi_start %29, %33 : !neura.data<i64, i1>, !neura.data<i64, i1> -> !neura.data<i64, i1>
// DATAFLOW-NEXT: %35 = "neura.constant"() <{value = 0 : i32}> : () -> !neura.data<index, i1>
// DATAFLOW-NEXT: %36 = "neura.gep"(%35, %34) <{operandSegmentSizes = array<i32: 0, 2>}> {lhs_value = @run_gemv_relu_gemv.y} : (!neura.data<index, i1>, !neura.data<i64, i1>) -> !neura.data<!llvm.ptr, i1>
// DATAFLOW-NEXT: %37 = "neura.load"(%36) : (!neura.data<!llvm.ptr, i1>) -> !neura.data<i32, i1>
// DATAFLOW-NEXT: %38 = "neura.add"(%37, %32) : (!neura.data<i32, i1>, !neura.data<i32, i1>) -> !neura.data<i32, i1>
// DATAFLOW-NEXT: %39 = "neura.add"(%34) {rhs_value = 1 : i64} : (!neura.data<i64, i1>) -> !neura.data<i64, i1>
// DATAFLOW-NEXT: %40 = "neura.icmp"(%39) <{cmpType = "eq"}> {rhs_value = 4 : i64} : (!neura.data<i64, i1>) -> !neura.data<i1, i1>
// DATAFLOW-NEXT: %41 = "neura.not"(%40) : (!neura.data<i1, i1>) -> !neura.data<i1, i1>
// DATAFLOW-NEXT: %42 = neura.grant_predicate %39, %41 : !neura.data<i64, i1>, !neura.data<i1, i1> -> !neura.data<i64, i1>
// DATAFLOW-NEXT: neura.ctrl_mov %42 -> %33 : !neura.data<i64, i1> !neura.data<i64, i1>
// DATAFLOW-NEXT: %43 = neura.grant_predicate %38, %41 : !neura.data<i32, i1>, !neura.data<i1, i1> -> !neura.data<i32, i1>
// DATAFLOW-NEXT: neura.ctrl_mov %43 -> %31 : !neura.data<i32, i1> !neura.data<i32, i1>
// DATAFLOW-NEXT: %44 = neura.grant_predicate %38, %40 : !neura.data<i32, i1>, !neura.data<i1, i1> -> !neura.data<i32, i1>
// DATAFLOW-NEXT: %45 = "neura.and"(%44) {rhs_value = 255 : i32} : (!neura.data<i32, i1>) -> !neura.data<i32, i1>
// DATAFLOW-NEXT: neura.return_value %45 : !neura.data<i32, i1>
// DATAFLOW-NEXT: neura.yield
// DATAFLOW-NEXT: }
0 test/c2llvm2mlir/nested_loop/kernel.cpp → ...ersion/c2llvm2mlir/nested_loop/kernel.cpp
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2 changes: 1 addition & 1 deletion test/c2llvm2mlir/nested_loop/test.mlir → ...version/c2llvm2mlir/nested_loop/test.mlir
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Expand Up @@ -22,7 +22,7 @@
// RUN: --fold-constant \
// RUN: --insert-data-mov \
// RUN: --map-to-accelerator="mapping-strategy=heuristic backtrack-config=simple" \
// RUN: --architecture-spec=../../arch_spec/architecture.yaml %t-kernel.mlir | FileCheck %s --check-prefix=CHECK-LLVM2NEURA-MAP
// RUN: --architecture-spec=../../../arch_spec/architecture.yaml %t-kernel.mlir | FileCheck %s --check-prefix=CHECK-LLVM2NEURA-MAP

// CHECK-LLVM2NEURA: accelerator = "neura"
// CHECK-LLVM2NEURA: %25 = neura.alloca %24 : !neura.data<i32, i1> -> !neura.data<!llvm.ptr, i1>
Expand Down
0 test/c2llvm2mlir/simple_loop/kernel.cpp → ...ersion/c2llvm2mlir/simple_loop/kernel.cpp
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4 changes: 2 additions & 2 deletions test/c2llvm2mlir/simple_loop/test.mlir → ...version/c2llvm2mlir/simple_loop/test.mlir
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Expand Up @@ -29,7 +29,7 @@
// RUN: --leverage-predicated-value \
// RUN: --transform-ctrl-to-data-flow \
// RUN: --view-op-graph \
// RUN: --architecture-spec=../../arch_spec/architecture.yaml \
// RUN: --architecture-spec=../../../arch_spec/architecture.yaml \
// RUN: --insert-data-mov %t-kernel.mlir -o %t-kernel-neura.mlir
// RUN: FileCheck %s --check-prefix=CHECK-LLVM2NEURA < %t-kernel-neura.mlir

Expand All @@ -43,7 +43,7 @@
// RUN: --leverage-predicated-value \
// RUN: --transform-ctrl-to-data-flow \
// RUN: --view-op-graph \
// RUN: --architecture-spec=../../arch_spec/architecture.yaml \
// RUN: --architecture-spec=../../../arch_spec/architecture.yaml \
// RUN: --insert-data-mov \
// RUN: --map-to-accelerator="mapping-strategy=heuristic backtrack-config=customized=5,3 dump-mapping-table=true" %t-kernel.mlir -o %t-kernel-mapped.mlir 2>&1 | tee %t-kernel-mapping-output.txt
// RUN: FileCheck %s --check-prefix=CHECK-MAPPING-TABLE < %t-kernel-mapping-output.txt
Expand Down
0 ...on/TosaToTaskflow/affine-to-taskflow.mlir → ...ion/tosa2taskflow/affine-to-taskflow.mlir
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0 ...onversion/TosaToTaskflow/tosa-fusion.mlir → ...Conversion/tosa2taskflow/tosa-fusion.mlir
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0 test/Conversion/TosaToTaskflow/tosa-opt.mlir → test/Conversion/tosa2taskflow/tosa-opt.mlir
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0 ...ersion/TosaToTaskflow/tosa-to-affine.mlir → ...version/tosa2taskflow/tosa-to-affine.mlir
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0 ...sion/TosaToTaskflow/tosa-to-taskflow.mlir → ...rsion/tosa2taskflow/tosa-to-taskflow.mlir
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