Minor changes to support clock gating

csail-csg · Apr 15, 2017 · dd96f4f · dd96f4f
1 parent e5d498a
commit dd96f4f
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/procs/riscy-lib/RVRFile.bsv b/procs/riscy-lib/RVRFile.bsv
@@ -34,7 +34,7 @@ interface ArchRFile;
 endinterface
 
 // This is a merged GPR/FPU register file
-(* synthesize *)
+(* synthesize, gate_all_clocks *)
 module mkArchRFile( ArchRFile );
     let verbose = False;
     File fout = stdout;
@@ -73,7 +73,7 @@ endmodule
 import RegUtil::*;
 
 // wr < {rd1, rd2, rd3}
-(* synthesize *)
+(* synthesize, gate_all_clocks *)
 module mkBypassArchRFile( ArchRFile );
     let verbose = False;
     File fout = stdout;

diff --git a/recycle-bsv-lib b/recycle-bsv-lib