[riscv64] Comment out any reading of cycles

cyring · Feb 24, 2025 · 04364b8 · 04364b8
1 parent 92c5e0f
commit 04364b8
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Showing 3 changed files with 22 additions and 19 deletions.
diff --git a/riscv64/corefreqd.c b/riscv64/corefreqd.c
@@ -2033,14 +2033,14 @@ REASON_CODE Child_Manager(REF *Ref)
 			Arg[cpu].TID = 0;
 		}
 	} else {
-		unsigned int seed32;
-		__asm__ volatile
+		unsigned int seed32 = time(0);
+/*TODO(Cycles)	__asm__ volatile
 		(
 			"csrr %0, mcycle"
 			: "=r" (seed32)
 			:
 			:
-		);
+		);*/
 	    #ifdef __GLIBC__
 		initstate_r(	seed32,
 				RO(Shm)->Cpu[cpu].Slice.Random.state,

diff --git a/riscv64/corefreqk.c b/riscv64/corefreqk.c
@@ -511,7 +511,7 @@ static void Query_Features(void *pArg)
 	iArg->Features->Info.Vendor.CRC = CRC_RESERVED;
 	iArg->SMT_Count = 1;
 	iArg->HypervisorID = HYPERV_NONE;
-/*TODO
+/*TODO(Cycles)
 	__asm__ __volatile__(
 		"csrr	%[cntfrq],	mcycle" "\n\t"
 		"fence iorw, iorw"
@@ -993,7 +993,8 @@ static void Query_DeviceTree(unsigned int cpu)
     if (max_freq > 0) {
 	FREQ2COF(max_freq, COF);
     } else {
-/*TODO	volatile unsigned long long cntfrq;
+/*TODO(Cycles)
+	volatile unsigned long long cntfrq;
 
 	__asm__ __volatile__(
 		"csrr	%[cntfrq],	mcycle" "\n\t"
@@ -1715,10 +1716,11 @@ static void Generic_Core_Counters_Clear(union SAVE_AREA_CORE *Save,
 
 #define Counters_Generic(Core, T)					\
 ({									\
-/*	RDTSC_COUNTERx3(Core->Counter[T].TSC,				\
-		**TODO	pmevcntr2_el0**mcycle,	Core->Counter[T].C0.UCC,\
-		**TODO	pmccntr_el0**mcycle,	Core->Counter[T].C0.URC,\
-		**TODO	pmevcntr3_el0**mcycle,	Core->Counter[T].INST );\
+/*TODO(Cycles)								\
+	RDTSC_COUNTERx3(Core->Counter[T].TSC,				\
+			pmevcntr2_el0:mcycle,	Core->Counter[T].C0.UCC,\
+			pmccntr_el0:mcycle,	Core->Counter[T].C0.URC,\
+			pmevcntr3_el0:mcycle,	Core->Counter[T].INST );\
 */									\
 	Core->Counter[T].INST &= INST_COUNTER_OVERFLOW;			\
 	/* Normalize frequency: */					\
@@ -1816,7 +1818,8 @@ static void Generic_Core_Counters_Clear(union SAVE_AREA_CORE *Save,
 
 #define PKG_Counters_Generic(Core, T)					\
 ({									\
-/*TODO	volatile unsigned long long cntpct; 				\
+/*TODO(Cycles)								\
+	volatile unsigned long long cntpct; 				\
 	__asm__ volatile						\
 	(								\
 		"csrr	%[cntpct],	mcycle"				\

diff --git a/riscv64/corefreqm.c b/riscv64/corefreqm.c
@@ -50,25 +50,25 @@ void CallWith_RDTSC_RDPMC(	RO(SHM_STRUCT) *RO(Shm),
 				unsigned long arg )
 {
 	struct SLICE_STRUCT *pSlice = &RO(Shm)->Cpu[cpu].Slice;
-
+/*TODO(Cycles)
 	RDTSC_PMCx1(	pSlice->Counter[0].TSC,
-			/*TODO:pmevcntr3_el0*/mcycle,
+			pmevcntr3_el0:mcycle,
 			pSlice->Counter[0].INST );
-
+*/
 	pSlice->Counter[0].INST &= INST_COUNTER_OVERFLOW;
-
+/*TODO(Cycles)
 	RDTSC_PMCx1(	pSlice->Counter[1].TSC,
-			/*TODO:pmevcntr3_el0*/mcycle,
+			pmevcntr3_el0:mcycle,
 			pSlice->Counter[1].INST );
-
+*/
 	pSlice->Counter[1].INST &= INST_COUNTER_OVERFLOW;
 
 	SliceFunc(RO(Shm), RW(Shm), cpu, arg);
-
+/*TODO(Cycles)
 	RDTSC_PMCx1(	pSlice->Counter[2].TSC,
-			/*TODO:pmevcntr3_el0*/mcycle,
+			pmevcntr3_el0:mcycle,
 			pSlice->Counter[2].INST );
-
+*/
 	pSlice->Counter[2].INST &= INST_COUNTER_OVERFLOW;
 
 	if (BITVAL(RW(Shm)->Proc.Sync, BURN)) {