[Intel] Mitigation mechanism: GDS_NO; RFDS_NO; MONITOR_MITG_NO

* Intel SDM Documentation Changes

x86_64/corefreq-api.h

@@ -1136,6 +1136,8 @@ typedef struct
 	BitCC	/* Intel */	OC_UTILIZED	__attribute__ ((aligned (16)));
 	BitCC	/* Intel */	OC_UNDERVOLT	__attribute__ ((aligned (16)));
 	BitCC	/* Intel */	OC_UNLOCKED	__attribute__ ((aligned (16)));
+	BitCC	/* Intel */	GDS_NO		__attribute__ ((aligned (16)));
+	BitCC	/* Intel */	RFDS_NO 	__attribute__ ((aligned (16)));
 
 	struct {
 		Bit64		Signal	__attribute__ ((aligned (8)));

x86_64/corefreq-cli-json.c

@@ -1853,6 +1853,10 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
 			json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.OC_UNDERVOLT);
 			json_key(&s, "OC_UNLOCKED");
 			json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.OC_UNLOCKED);
+			json_key(&s, "GDS_NO");
+			json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.GDS_NO);
+			json_key(&s, "RFDS_NO");
+			json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.RFDS_NO);
 			json_key(&s, "IPRED_DIS_U");
 			json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.IPRED_DIS_U);
 			json_key(&s, "IPRED_DIS_S");
@@ -1867,6 +1871,8 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
 			json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.DDPD_U_DIS);
 			json_key(&s, "MCDT_NO");
 			json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.MCDT_NO);
+			json_key(&s, "MONITOR_MITG_NO");
+			json_literal(&s, "%llu", RO(Shm)->Proc.Mechanisms.MONITOR_MITG_NO);
 			json_key(&s, "BTC_NO");
 			json_literal(&s, "%llu", RO(Shm)->Proc.Features.leaf80000008.EBX.BTC_NO);
 			json_key(&s, "BTC_NOBR");

x86_64/corefreq-cli-rsc-en.h

@@ -2090,13 +2090,16 @@
 #define RSC_MECH_BHI_NO_CODE_EN 	"Arch - No Branch Target Injection"
 #define RSC_MECH_XAPIC_DIS_CODE_EN	"Arch - Legacy xAPIC Disable"
 #define RSC_MECH_PBRSB_NO_CODE_EN "Arch - No Post-Barrier Return Stack Buffer"
+#define RSC_MECH_GDS_NO_CODE_EN 	"Arch - No Gather Data Sampling"
+#define RSC_MECH_RFDS_NO_CODE_EN	"Arch - No Register File Data Sampling"
 #define RSC_MECH_IPRED_DIS_U_CODE_EN	"Arch - IPRED disabled for CPL3"
 #define RSC_MECH_IPRED_DIS_S_CODE_EN	"Arch - IPRED disabled for CPL0/1/2"
 #define RSC_MECH_RRSBA_DIS_U_CODE_EN	"Arch - RRSBA disabled for CPL3"
 #define RSC_MECH_RRSBA_DIS_S_CODE_EN	"Arch - RRSBA disabled for CPL0/1/2"
 #define RSC_MECH_DDPD_U_DIS_CODE_EN	"Arch - Data Dependent Prefetcher CPL3"
 #define RSC_MECH_BHI_DIS_S_CODE_EN	"Arch - BHI disabled for CPL0/1/2"
 #define RSC_MECH_MCDT_NO_CODE_EN "No MXCSR Configuration Dependent Timing"
+#define RSC_MECH_UMON_MITG_NO_CODE_EN	"No MONITOR/UMONITOR mitigation"
 #define RSC_MECH_BTC_NO_CODE_EN 	"No Branch Type Confusion"
 #define RSC_MECH_BTC_NOBR_CODE_EN 	"BTC on Non-Branch instruction"
 #define RSC_MECH_XPROC_LEAK_CODE_EN  "Arch - Cross Processor Information Leak"

x86_64/corefreq-cli-rsc-fr.h

@@ -1564,13 +1564,16 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
 #define RSC_MECH_BHI_NO_CODE_FR 	RSC_MECH_BHI_NO_CODE_EN
 #define RSC_MECH_XAPIC_DIS_CODE_FR	RSC_MECH_XAPIC_DIS_CODE_EN
 #define RSC_MECH_PBRSB_NO_CODE_FR	RSC_MECH_PBRSB_NO_CODE_EN
+#define RSC_MECH_GDS_NO_CODE_FR 	RSC_MECH_GDS_NO_CODE_EN
+#define RSC_MECH_RFDS_NO_CODE_FR	RSC_MECH_RFDS_NO_CODE_EN
 #define RSC_MECH_IPRED_DIS_U_CODE_FR	RSC_MECH_IPRED_DIS_U_CODE_EN
 #define RSC_MECH_IPRED_DIS_S_CODE_FR	RSC_MECH_IPRED_DIS_S_CODE_EN
 #define RSC_MECH_RRSBA_DIS_U_CODE_FR	RSC_MECH_RRSBA_DIS_U_CODE_EN
 #define RSC_MECH_RRSBA_DIS_S_CODE_FR	RSC_MECH_RRSBA_DIS_S_CODE_EN
 #define RSC_MECH_DDPD_U_DIS_CODE_FR	RSC_MECH_DDPD_U_DIS_CODE_EN
 #define RSC_MECH_BHI_DIS_S_CODE_FR	RSC_MECH_BHI_DIS_S_CODE_EN
 #define RSC_MECH_MCDT_NO_CODE_FR	RSC_MECH_MCDT_NO_CODE_EN
+#define RSC_MECH_UMON_MITG_NO_CODE_FR	RSC_MECH_UMON_MITG_NO_CODE_EN
 #define RSC_MECH_BTC_NO_CODE_FR 	RSC_MECH_BTC_NO_CODE_EN
 #define RSC_MECH_BTC_NOBR_CODE_FR 	RSC_MECH_BTC_NOBR_CODE_EN
 #define RSC_MECH_XPROC_LEAK_CODE_FR	RSC_MECH_XPROC_LEAK_CODE_EN

x86_64/corefreq-cli-rsc.c

@@ -2082,13 +2082,16 @@ RESOURCE_ST Resource[] = {
 	LDT(RSC_MECH_BHI_NO),
 	LDT(RSC_MECH_XAPIC_DIS),
 	LDT(RSC_MECH_PBRSB_NO),
+	LDT(RSC_MECH_GDS_NO),
+	LDT(RSC_MECH_RFDS_NO),
 	LDT(RSC_MECH_IPRED_DIS_U),
 	LDT(RSC_MECH_IPRED_DIS_S),
 	LDT(RSC_MECH_RRSBA_DIS_U),
 	LDT(RSC_MECH_RRSBA_DIS_S),
 	LDT(RSC_MECH_DDPD_U_DIS),
 	LDT(RSC_MECH_BHI_DIS_S),
 	LDT(RSC_MECH_MCDT_NO),
+	LDT(RSC_MECH_UMON_MITG_NO),
 	LDT(RSC_MECH_BTC_NO),
 	LDT(RSC_MECH_BTC_NOBR),
 	LDT(RSC_MECH_XPROC_LEAK),

x86_64/corefreq-cli-rsc.h

@@ -1885,13 +1885,16 @@ enum {
 	RSC_MECH_BHI_NO,
 	RSC_MECH_XAPIC_DIS,
 	RSC_MECH_PBRSB_NO,
+	RSC_MECH_GDS_NO,
+	RSC_MECH_RFDS_NO,
 	RSC_MECH_IPRED_DIS_U,
 	RSC_MECH_IPRED_DIS_S,
 	RSC_MECH_RRSBA_DIS_U,
 	RSC_MECH_RRSBA_DIS_S,
 	RSC_MECH_DDPD_U_DIS,
 	RSC_MECH_BHI_DIS_S,
 	RSC_MECH_MCDT_NO,
+	RSC_MECH_UMON_MITG_NO,
 	RSC_MECH_BTC_NO,
 	RSC_MECH_BTC_NOBR,
 	RSC_MECH_XPROC_LEAK,

x86_64/corefreq-cli.c

@@ -3497,6 +3497,22 @@ REASON_CODE SysInfoFeatures(	Window *win,
 		width - 23 - RSZ(MECH_PBRSB_NO),
 		MECH
 	},
+	{
+		(unsigned int[]) { CRC_INTEL, 0 },
+		RO(Shm)->Proc.Mechanisms.GDS_NO,
+		attr_Feat,
+		2, "%s%.*sGDS_NO   [%7s]", RSC(MECH_GDS_NO).CODE(),
+		width - 21 - RSZ(MECH_GDS_NO),
+		MECH
+	},
+	{
+		(unsigned int[]) { CRC_INTEL, 0 },
+		RO(Shm)->Proc.Mechanisms.RFDS_NO,
+		attr_Feat,
+		2, "%s%.*sRFDS_NO   [%7s]", RSC(MECH_RFDS_NO).CODE(),
+		width - 22 - RSZ(MECH_RFDS_NO),
+		MECH
+	},
 	{
 		(unsigned int[]) { CRC_INTEL, 0 },
 		RO(Shm)->Proc.Mechanisms.IPRED_DIS_U,
@@ -3553,6 +3569,14 @@ REASON_CODE SysInfoFeatures(	Window *win,
 		width - 22 - RSZ(MECH_MCDT_NO),
 		MECH
 	},
+	{
+		(unsigned int[]) { CRC_INTEL, 0 },
+		RO(Shm)->Proc.Mechanisms.MONITOR_MITG_NO,
+		attr_Feat,
+		2, "%s%.*sUMON_MITG_NO   [%7s]", RSC(MECH_UMON_MITG_NO).CODE(),
+		width - 27 - RSZ(MECH_UMON_MITG_NO),
+		MECH
+	},
 	{
 		(unsigned int[]) { CRC_AMD, CRC_HYGON, 0 },
 		RO(Shm)->Proc.Mechanisms.XPROC_LEAK,

x86_64/corefreq.h

@@ -426,7 +426,10 @@ typedef struct
 				OC_UTILIZED	: 20-18,
 				OC_UNDERVOLT	: 22-20,
 				OC_UNLOCKED	: 24-22,
-				_UnusedMechBits : 64-24;
+				MONITOR_MITG_NO : 25-24,
+				GDS_NO		: 27-25,
+				RFDS_NO 	: 29-27,
+				_UnusedMechBits : 64-29;
 	} Mechanisms;
 
 	enum THERMAL_FORMULAS	thermalFormula;

x86_64/corefreqd.c

@@ -1892,6 +1892,14 @@ void Mitigation_1st_Stage(	RO(SHM_STRUCT) *RO(Shm),
 						RW(Proc)->OC_UNLOCKED,
 						RO(Proc)->ARCH_CAP_Mask),
 
+			GDS_NO = BITCMP_CC(	LOCKLESS,
+						RW(Proc)->GDS_NO,
+						RO(Proc)->ARCH_CAP_Mask ),
+
+			RFDS_NO = BITCMP_CC(	LOCKLESS,
+						RW(Proc)->RFDS_NO,
+						RO(Proc)->ARCH_CAP_Mask ),
+
 			IPRED_DIS_U = BITCMP_CC(LOCKLESS,
 						RW(Proc)->IPRED_DIS_U,
 						RO(Proc)->SPEC_CTRL_Mask),
@@ -2047,6 +2055,16 @@ void Mitigation_1st_Stage(	RO(SHM_STRUCT) *RO(Shm),
 		+ (2 * OC_UNLOCKED)
 	);
 
+	RO(Shm)->Proc.Mechanisms.GDS_NO = (
+		RO(Shm)->Proc.Features.ExtFeature.EDX.IA32_ARCH_CAP
+		+ (2 * GDS_NO)
+	);
+
+	RO(Shm)->Proc.Mechanisms.RFDS_NO = (
+		RO(Shm)->Proc.Features.ExtFeature.EDX.IA32_ARCH_CAP
+		+ (2 * RFDS_NO)
+	);
+
 	RO(Shm)->Proc.Mechanisms.IPRED_DIS_U = (
 	      (RO(Shm)->Proc.Features.ExtFeature.EAX.MaxSubLeaf >= 2)
 	   && (RO(Shm)->Proc.Features.ExtFeature_Leaf2_EDX.IPRED_SPEC_CTRL == 1)
@@ -2086,6 +2104,10 @@ void Mitigation_1st_Stage(	RO(SHM_STRUCT) *RO(Shm),
 	RO(Shm)->Proc.Mechanisms.MCDT_NO = (
 		RO(Shm)->Proc.Features.ExtFeature_Leaf2_EDX.MCDT_NO == 1
 	);
+
+	RO(Shm)->Proc.Mechanisms.MONITOR_MITG_NO = (
+		RO(Shm)->Proc.Features.ExtFeature_Leaf2_EDX.MONITOR_MITG_NO == 1
+	);
     }
     else if (	(RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_AMD)
 	||	(RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_HYGON) )

x86_64/corefreqk.c

@@ -12392,6 +12392,16 @@ static void Intel_Mitigation_Mechanisms(CORE_RO *Core)
 		BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->OC_UNLOCKED, Core->Bind);
 	    }
 	}
+	if (Arch_Cap.GDS_NO) {
+		BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->GDS_NO, Core->Bind);
+	} else {
+		BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->GDS_NO, Core->Bind);
+	}
+	if (Arch_Cap.RFDS_NO) {
+		BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->RFDS_NO, Core->Bind);
+	} else {
+		BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->RFDS_NO, Core->Bind);
+	}
     }
     if (PUBLIC(RO(Proc))->Features.ExtFeature.EDX.IA32_CORE_CAP)
     {
@@ -12810,6 +12820,8 @@ static void PerCore_Reset(CORE_RO *Core)
 	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->OC_UTILIZED, Core->Bind);
 	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->OC_UNDERVOLT, Core->Bind);
 	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->OC_UNLOCKED, Core->Bind);
+	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->GDS_NO	, Core->Bind);
+	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->RFDS_NO	, Core->Bind);
 
 	BITWISECLR(LOCKLESS, Core->ThermalPoint.Mask);
 	BITWISECLR(LOCKLESS, Core->ThermalPoint.Kind);

x86_64/coretypes.h

@@ -1283,7 +1283,8 @@ typedef struct THERMAL_POWER_LEAF
 		HWP_Fast	: 19-18,/* IA32_HWP_REQUEST MSR fast access */
 		HWFB_Cap	: 20-19,/* IA32 HW_FEEDBACK* MSR support */
 		HWP_Idle	: 21-20,/* Ignore (or not) Idle SMT Processor */
-		Reserved3	: 23-21,
+		Reserved3	: 22-21,
+		HWP_Ctl 	: 23-22, /* IA32_HWP_CTL MSR support	*/
 		ITD_MSR 	: 24-23, /* HW_FEEDBACK_{CHAR,THREAD_CONFIG} */
 		THERM_INT_MSR	: 25-24, /* IA32_THERM_INTERRUPT MSR	*/
 		Reserved4	: 32-25;
@@ -1509,7 +1510,9 @@ typedef struct	/* Extended Feature Flags Leaf equal or greater than 2	*/
 		DDPD_U_SPEC_CTRL:  4-3,
 		BHI_SPEC_CTRL	:  5-4,
 		MCDT_NO 	:  6-5,
-		Reserved	: 32-6;
+		Reserved1	:  7-6,
+		MONITOR_MITG_NO :  8-7,
+		Reserved2	: 32-8;
 	} EDX;
 } CPUID_0x00000007_2;
 

x86_64/intel_reg.h

@@ -380,6 +380,14 @@
 	#define MSR_IA32_HWP_REQUEST		MSR_HWP_REQUEST
 #endif
 
+#ifndef MSR_HWP_CTL
+	#define MSR_HWP_CTL			0x00000776
+#endif
+
+#ifndef MSR_HWP_STATUS
+	#define MSR_HWP_STATUS			0x00000777
+#endif
+
 #ifndef MSR_IA32_XSS
 	#define MSR_IA32_XSS			0x00000da0
 #endif
@@ -595,7 +603,13 @@ typedef union
 		ReservedBits2		: 23-22,
 		OVERCLOCKING_STATUS_MSR : 24-23, /* IA32_OVERLOCKING_STATUS */
 		PBRSB_NO		: 25-24,
-		ReservedBits3		: 64-25;
+		GDS_CTRL		: 26-25, /* IA32_MCU_OPT_CTRL MSR */
+		GDS_NO			: 27-26, /* Gather Data Sampling */
+		RFDS_NO 		: 28-27, /*Register File Data Sampling*/
+		RFDS_CLEAR		: 29-28,
+		IGN_UMONITOR_SUPPORT	: 30-29, /* IA32_MCU_OPT_CTRL bit 6 */
+		MON_UMON_MITG_SUPPORT	: 31-30, /* IA32_MCU_OPT_CTRL bit 7 */
+		ReservedBits3		: 64-31;
 	};
 } ARCH_CAPABILITIES;
 
@@ -631,7 +645,11 @@ typedef union
 		_RTM_ALLOW	:  2-1, /*1: XBEGIN=IA32_TSX_CTRL[RTM_DISABLE]*/
 		_RTM_LOCKED	:  3-2, /*1: RTM_ALLOW is locked at zero */
 		_FB_CLEAR_DIS	:  4-3, /* VERW instruction will not perform */
-		ReservedBits	: 64-4;
+		_GDS_MITG_DIS	:  5-4,
+		_GDS_MITG_LOCK	:  6-5,
+		_IGN_UMONITOR	:  7-6,
+		_MON_UMON_MITG	:  8-7,
+		ReservedBits	: 64-8;
 	};
 } MCU_OPT_CTRL;	/* Microcode Update Option Control (R/W)		*/